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M35046-059FP Datasheet(PDF) 6 Page - Mitsubishi Electric Semiconductor

No. de pieza M35046-059FP
Descripción Electrónicos  SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
PDF  40 Pages
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Fabricante Electrónico  MITSUBISHI [Mitsubishi Electric Semiconductor]
Página de inicio  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

M35046-059FP Datasheet(HTML) 6 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI MICROCOMPUTERS
M35046-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
6
(2) Address 12116
Contents
Status
Function
Register
DA
Remarks
P0 output (port P0). Port data is set by PTD0.
BLNK0 output. Polarity is set by PTD0.
P1 output (port P1). Port data is set by PTD1.
R signal output. Polarity is set by PTD1.
P2 output (port P2). Port data is set by PTD2.
Can not be used.
P3 output (port P3). Port data is set by PTD3.
G signal output. Polarity is set by PTD3.
P4 output (port P4). Port data is set by PTD4.
Can not be used.
P5 output (port P5). Port data is set by PTD5.
B signal output. Polarity is set by PTD5.
“L” output (P0 output) or negative polarity output (BLNK0 output).
“H” output (P0 output) or positive polarity output (BLNK0 output).
“L” output (P1 output) or negative polarity output (R signal output).
“H” output (P1 output) or positive polarity output (R signal output).
“L” output (P2 output).
“H” output (P2 output).
“L” output (P3 output) or negative polarity output (G signal output).
“H” output (P3 output) or positive polarity output (G signal output).
“L” output (P2 output).
“H” output (P2 output).
“L” output (P5 output) or negative polarity output (B signal output).
“H” output (P5 output) or positive polarity output (B signal output).
“L” output (P6 output).
“H” output (P6 output).
“L” output (P7 output).
“H” output (P7 output).
For details, see (2) Setting display frequencies under Register
Supplementary Description.
To be used when EXCK0=1 and EXCK1=1.
BLNK0 outputs blanking signal.
Blanking status is determined by BLK0,
BLK1, and DSP0 to DSP11 settings.
P0 pin data control.
P1 pin data control.
P2 pin exclusive port output state con-
trol.
P3 pin data control.
P4 pin exclusive port output state con-
trol.
P5 pin data control.
P6 pin exclusive port output state con-
trol.
P7 pin exclusive port output state con-
trol.
Set display frequency area.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
Note. To determined this register, input clock (at least one clock) to the external clock pin (TCK).
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTD0
PTD1
PTD2
PTD3
PTD4
PTD5
PTD6
PTD7
RSEL0



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