DRV5053_15 datasheet(11/24 Pages) TI

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DRV5053

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SLIS153B – MAY 2014 – REVISED SEPTEMBER 2014

Feature Description (continued)

8.3.4 Output Stage

The DRV5053 output stage is capable of up to 300 µA of current source or 2.3 mA sink.

For proper operation, ensure that equivalent output load ROUT > 10 k

Ω. In addition, ensure that the load

capacitance COUT < 10 nF.

8.3.5 Protection Circuits

An analog current limit circuit limits the current through the output driver. The driver current will be clamped to

IOCP

8.3.5.1 Overcurrent Protection (OCP)

An analog current-limit circuit limits the current through the FET. The driver current is clamped to IOCP. During

this clamping, the rDS(on) of the output FET is increased from the nominal value.

8.3.5.2 Load Dump Protection

The DRV5053 device operates at DC VCC conditions up to 38 V nominally, and can additionally withstand VCC =

40 V. No current-limiting series resistor is required for this protection.

8.3.5.3 Reverse Supply Protection

The DRV5053 device is protected in the event that the VCC pin and the GND pin are reversed (up to –22 V).

NOTE

In a reverse supply condition, the OUT pin reverse-current must not exceed the ratings

specified in the Absolute Maximum Ratings.

FAULT

CONDITION

DEVICE

DESCRIPTION

RECOVERY

FET overload (OCP)

ISINK ≥ IOCP

Operating

Output current is clamped to IOCP

IO < IOCP

Load Dump

38 V < VCC < 40 V

Operating

Device will operate for a transient duration

VCC ≤ 38 V

Reverse Supply

–22 V < VCC < 0 V

Disabled

Device will survive this condition

VCC ≥ 2.5 V

8.4 Device Functional Modes

The DRV5053 device is active only when VCC is between 2.5 and 38 V.

When a reverse supply condition exists, the device is inactive.

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