PIC16LC712 datasheet(37/108 Pages) MICROCHIP

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PIC16C712/716

Preliminary

DS41106A-page 37

6.1

Timer2 Operation

Timer2 can be used as the PWM time-base for PWM

mode of the CCP module.

The TMR2 register is readable and writable, and is

cleared on any device reset.

The input clock (FOSC/4) has a prescale option of 1:1,

1:4

1:16,

selected

control

bits

T2CKPS1:T2CKPS0 (T2CON<1:0>).

The match output of TMR2 goes through a 4-bit

postscaler (which gives a 1:1 to 1:16 scaling inclusive)

to generate a TMR2 interrupt (latched in flag bit

TMR2IF, (PIR1<1>)).

The prescaler and postscaler counters are cleared

when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device reset (Power-on Reset, MCLR reset,

Watchdog Timer reset, or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

6.2

Timer2 Interrupt

The Timer2 module has an 8-bit period register PR2.

Timer2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readable and writable register. The PR2 register is ini-

tialized to FFh upon reset.

TABLE 6-1

REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

resets

0Bh,8Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

—

ADIF

—

CCP1IF

TMR2IF

TMR1IF

-00- -000

0000 -000

8Ch

PIE1

—

ADIE

—

CCP1IE

TMR2IE

TMR1IE

-0-- -000

0000 -000

11h

TMR2

Timer2 module’s register

0000 0000

12h

T2CON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0

TMR2ON

T2CKPS1

T2CKPS0

-000 0000

92h

PR2

Timer2 Period Register

1111 1111

Legend:

= unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.

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