ML4822

7

Q1 Turn-On

The turn-on event consists of the time it takes for the

current through L2 to ramp to the L1 current plus the

resonant event of L2 and the ZVS capacitor. The total

event should occur in a minimum of 350–450ns, but can

be longer at the risk of increasing the total harmonic

distortion. Setting these times equal should minimize

conducted and radiated emissions.

(1)

The value of L2 is calculated to remain in discontinuous-

mode:

L

VV

t

P

BUS

RMS MIN

IL

OUT

2

2

2

=

××

×

()

(2)

The resonant event occurs in 1/4 of a full sinusoidal cycle.

For example, when a 1/4 cycle occurs in 200ns, the

frequency is 1.25MHz.

f

LC

t

RES

ZVS

RES

=

×

=

×

1

22

1

4

π

(3)

Rearranging and solving for L2:

L

t

C

RES

ZVS

2

4

2

2

=

×

×

π

(4)

equations 2 and 4 equal to each other and solving for

C

tP

VV

t

ZVS

RES

OUT

BUS

RMS MIN

IL

=

××

×

××

×

42

2

2

2

π

()

(5)

APPLICATION

Figure 3 displays a typical application circuit for a 500W

ZVS PFC supply. Full design details are covered in

application note 33, ML4822 Power Factor Correction

With Zero Voltage Resonant Switching.

Figure 2. Timing Diagrams

A. SYSTEM

CLOCK

(INTERNAL)

B. RTCT

C. ZVS GATE (Q2)

D. VDS (Q2)

E. PFC GATE (Q1)

F. VDS (Q1)