ASM5P2304A

http://onsemi.com

2

Figure 1. Block Diagram

PLL

/2

Extra Divider (−2)

CLKA2

CLKA1

FBK

CLKB1

CLKB2

REF

Table 1. ASM5P2304A CONFIGURATIONS

Device

Feedback From

Bank A Frequency

Bank B Frequency

ASM5P2304A (−1, 1H)

Bank A or Bank B

Reference

Reference

ASM5P2304A (−2, −2H)

Bank A

Reference

Reference /2

ASM5P2304A (−2, −2H)

Bank B

2 x Reference

Reference

Zero Delay and Skew Control

For applications requiring zero input−output delay, all outputs must be equally loaded.

1500

1000

500

0

−500

−1000

−1500

30

25

20

15

10

5

−5

−10

−15

−20

−25

−30

Output Load Difference: FBK Load − CLKA/CLKB Load (pF)

Figure 2. REF Input to CLKA/CLKB Delay vs. Difference in Loading

between FBK Pin and CLKA/CLKB Pins

0

To close the feedback loop of the ASM5P2304A, the FBK

pin can be driven from any of the four available clock

outputs. The output driving the FBK pin will be driving a

total load of 7 pF plus any additional load that it drives. The

relative loading of this output (with respect to the remaining

outputs) can adjust the input−output delay. This is shown in

the above graph.

For applications requiring zero input−output delay, all

outputs including the one providing feedback should be

equally loaded. If input−output delay adjustments are

required, use the above graph to calculate loading

differences between the feedback output and remaining

outputs. For zero output−output skew, be sure to load outputs

equally.