ACE9030

5

Parameter

Min.

Typ.

Max.

Unit

Conditions

Power supply

Supply current, Radio Interface:

Sleep mode

2.3

2·7

mA

XO, OSC8 on

Fully operating (excluding I

7

mA

(see Note 1)

Supply current, Synthesisers: V

f

REF

= 10 MHz

Main and Auxiliary ON

5

mA

f

Main ON and Auxiliary in Standby

3.7

mA

f

AUX

= 10 MHz

Main in Standby and Auxiliary ON

3

mA

(see Note 2)

Main and Auxiliary in Standby, with Bandgap off

100

µA

Supply current, Synthesisers:

f

REF

= 15 MHz

Main and Auxiliary ON

3

mA

f

Main ON and Auxiliary in Standby

2

mA

f

AUX

= 90 MHz

Main in Standby and Auxiliary ON

2

mA

(see Note 2)

Main and Auxiliary in Standby

100

µA

Input and output signals

Logic input HIGH (LATCHC, LATCHB, DATA,

CL, and TEST)

0·7 x V

DD

V

V

Logic input LOW (LATCHC, LATCHB, DATA,

CL, and TEST)

– 0·3

+ 0·8

V

Input capacitance (signal pins)

10

pF

Pin voltage

Input leakage (signal pins)

1

µAV

Logic output HIGH (RXCD, DATA, AFCOUT,

V

V

TEST and DOUT2, 3 and 4)

External load:

Logic output LOW (RXCD, DATA, AFCOUT,

0·4

V

20 k

Ω & 30 pF

TEST and DOUT2, 3 and 4)

Output ON level, DOUT0 and DOUT1

V

V

I

Output HIGH level, DOUT5, 6 and 7

2·3

2·9

V

I

Output LOW level, DOUT5, 6 and 7

0·3

V

I

Trimmed output level ON, DOUT8

3·35

3·55

V

I

Level difference, DOUT8 ON – ADC reference

– 5

+ 15

mV

Output level OFF, DOUT8

0.4

V

MODMP, MODMN output HIGH

V

V

V

I

MODMP, MODMN output LOW

V

V

V

I

Input Schmitt Hysteresis, pins CL, LATCHB,

0·3

V

LATCHC, DATA.

Analog circuits bias resistor on I

REF

68

k

Ω

V

100

k

Ω

V

ELECTRICAL CHARACTERISTICS

These characteristics apply over these ranges of conditions (unless otherwise stated):

T

= + 3·6 to + 5·0 V, GND ref. = V

SS

D.C. Characteristics

Notes

1. The sleep current is specified with the crystal oscillator (XO) and the OSC8 oscillator and PLL running as these are normally needed to provide

the clock to the system controller.

2. The terms f

inputs (pins FIM and FIMB) and the Auxiliary synthesiser inputs (pins FIA and FIAB) respectively.