ISO-CMOS

MT8982

2-35

into RxD by the rising edges of the next eight SCLK

cycles. If the operation is a read, eight data bits are

clocked from TxD by the falling edges of the next

eight SCLK cycles. The rising edge of CS tristates

TxD after the last transmitted bit.

Successive write microcycles can take place while

CS remains low, with each microcycle following the

sequence of a command/address byte followed by a

data byte. CS must go high after a read microcycle.

Note that a command/address byte must always

follow the high to low transition on CS.

When the MPS input is pulled high and the CS input

is pulled low, the microport is put into serial bus

mode. Pins RxD and SCLK become CSTi0 and

CSTi1, respectively, and are configured as 2048 kbit/

s serial streams with 32 channels each. The frame

and timeslot boundaries are determined by F0i and

C4. Each channel on CSTi0 and CSTi1 is stored in

the connect memory address corresponding to the

link and channel number. The Data Memory and the

Connect Memory cannot be read when the microport

is in serial bus mode.

Device Timing

During each TDM timeslot, eight read or write

operations occur internally in the MT8982. These are

shown in Figure 4. During the first two bit periods,

data received in the previous timeslot on the two

input TDM streams is loaded into the Data Memory.

Bit periods 2 and 6 are serial microport access

windows; data may be read from, or written to any

accessible memory location.

During bit periods 3

and 5, data is read from the connect memory for the

next timeslot on links 0 and 1 respectively. The Data

Memory locations which are addressed by the

previous reads of the connect memory are accessed

during bit periods 4 and 7.

When the microport is in serial bus mode, bit periods

2 and 6 have a slightly different function. Data from

the

previous

timeslot

of

CSTi0

and

CSTi1

respectively is written to the corresponding connect

memory locations.

The transfer of information from the input TDM

streams to the output TDM streams results in a delay

through the MT8982. This delay is dependent only

on the combination of source and destination

Table 1. Command Address Byte

Table 2. Connect Memory Connection Mode Data Byte

Bit

Name

Description

7

Stream

Stream. This is the most significant bit of the address for the memory location that

is to be accessed. It corresponds to one of the TDM serial streams (0-1).

2-6

Ch0-Ch4

Channel 0-4. These bits are the five least significant bits of the address for the

memory location that is to be accessed. The binary value of these bits correspond

to a TDM channel (0-31).

0-1

Cmd0-Cmd1

Command Select 0-1. These two bits define the four command operations for the

MT8982. The destination addressed by the command is defined in bits 2-7 of the

Command/Address byte.

Cmd0-Cmd1

0-0

Read from Connect Memory.

0-1

Write to Connect Memory and set connection mode.

1-0

Read Data Memory.

1-1

Write to Connect Memory and set message mode.

Bit

Name

Description

7

NA

Unused.

6

ODE

Output Drive Enable. When this bit is set, the addressed TDM channel is placed

in tristate. When low, the output is enabled.

5

STi

Input Stream. This bit defines the input TDM stream from which the output data is

sourced (0-1).

0-4

SC0-SC4

Source Channel 0-4. The binary value of these bits defines the input channel from

which the output data is sourced (0-31).