VP211

5

Device Description

The VP211 is a dual 90MHz 6-bit ADC system, (see

Fig.2). Included on chip is a high bandwidth ADC driver

amplifier, a 6-bit analog to digital converter, latches and TTL

compatible data outputs. The VP211 also has the necessary

bias voltages for the reference resistor chain in the ‘flash’

architecture of the ADC.

Analog Input

The analog inputs, (VIN A,B) are A.C. coupled into the

non-inverting input of the ADC driver amplifiers, which

provide the necessary bandwidth, gain, offset and low

impedance required to drive the ADC. The amplifier has

been designed so that an input of 0 volts will produce an

output level equal to the voltage present at the middle of the

ADC resistor chain, VRM (3.00V typ.). This is achieved by an

internal feedback loop within each amplifier which compares

the amplifier output with VRM, (see Fig.3). This voltage will

produce a transition binary code of 011111 to 100000 at the

output of the ADC.

Reference Voltage

An on chip band gap voltage reference circuit combined

with two op-amps provides all the necessary bias voltages

for the ADC reference resistor chain, bottom (VRB), middle

(VRM) and top(VRT). VRB, VRM and VRT have been

brought out to pins 12, 9 and 4 respectively and should be

decoupled with 100nF capacitors close to the package pins.

ADC Circuit

The VP211 employs a ‘flash’ architecture consisting of a

reference resistor chain, an array of 64 comparators,

encoding logic and a 6-bit latch. The 63 reference levels

generated by the resistor chain are compared with the

analog output signal from the ADC driver amplifier using the

comparator array. This produces a thermometer code which

the encoding logic converts into a 6-bit word.

Digital Interface

The TTL data output pins, (DA0-DA5) and (DB0-DB5),

have been optimized to interface with devices in close

proximity to the VP211 and are designed to provide

satisfactory logic levels at speeds up to 90MHz into a fanout

of one and a total load capacitance of 10pF. All data outputs

should have approximately equivalent loading to ensure

proper setup and hold times. For capacitive loads in excess

of 10pF, output buffers are recommended.

Clock Interface

The clock signal to the ADC synchronizes the sampling,

conversion and output stages of the device as shown in the

timing diagram (see Fig.4). The output of the ADC driver amp

is sampled when the comparator array is latched on the rising

edge of the input clock. Data is then presented to the TTL data

outputs and latched on the falling edge of the input clock.

INPUT

SIGNAL

VRM

TO ADC

ADC DRIVER

AMP

COMP_(Q,I)

DC SHIFT

Fig.3 DC offset internal feedback loop

C

Latch

Comparator

L

V ref.

VIN(A,B)

Clock to ADC

Data Out

CLKIN

Data Outputs

TTL

Threshold

Tpw 1

Tpw 0

VIN(A,B)

N

N+1

N-1

N+1

N

N-1

Tsu

Fig.4 System timing diagram