PIC16F72SLASHML datasheet(16/136 Pages) MICROCHIP

16 / 136 page

PIC16F72

DS39597B-page 14

 2002 Microchip Technology Inc.

2.2.2.3

INTCON Register

The INTCON Register is a readable and writable regis-

ter that contains various enable and flag bits for the

TMR0 register overflow, RB Port change and External

RB0/INT pin interrupts.

INTCON: INTERRUPT CONTROL REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)

Note:

Interrupt flag bits get set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

R/W-0

R/W-x

GIE

PEIE

TMR0IE

INTE

RBIE

TMR0IF

INTF

RBIF

bit 7

bit 0

bit 7

GIE: Global Interrupt Enable bit

= Enables all unmasked interrupts

= Disables all interrupts

bit 6

PEIE: Peripheral Interrupt Enable bit

= Enables all unmasked peripheral interrupts

= Disables all peripheral interrupts

bit 5

TMR0IE: TMR0 Overflow Interrupt Enable bit

= Enables the TMR0 interrupt

= Disables the TMR0 interrupt

bit 4

INTE: RB0/INT External Interrupt Enable bit

= Enables the RB0/INT external interrupt

= Disables the RB0/INT external interrupt

bit 3

RBIE: RB Port Change Interrupt Enable bit

= Enables the RB port change interrupt

= Disables the RB port change interrupt

bit 2

TMR0IF: TMR0 Overflow Interrupt Flag bit

= TMR0 register has overflowed (must be cleared in software)

= TMR0 register did not overflow

bit 1

INTF: RB0/INT External Interrupt Flag bit

= The RB0/INT external interrupt occurred (must be cleared in software)

= The RB0/INT external interrupt did not occur

bit 0

RBIF: RB Port Change Interrupt Flag bit

A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch

condition and allow flag bit RBIF to be cleared.

= At least one of the RB7:RB4 pins changed state (must be cleared in software)

= None of the RB7:RB4 pins have changed state

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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