54ABT646

Outputs

General Description

The ’ABT646 consists of bus transceiver circuits with

TRI-STATE, D-type flip-flops, and control circuitry arranged

for multiplexed transmission of data directly from the input

bus or from the internal registers. Data on the A or B bus will

be clocked into the registers as the appropriate clock pin

goes to a high logic level. Control OE and direction pins are

provided to control the transceiver function. In the trans-

ceiver mode, data present at the high impedance port may

be stored in either the A or the B register or in both. The se-

lect controls can multiplex stored and real-time (transparent

mode) data. The direction control determines which bus will

receive data when the enable control OE is Active LOW. In

the isolation mode (control OE HIGH), A data may be stored

in the B register and/or B data may be stored in the A regis-

ter.

Features

n Independent registers for A and B buses

n Multiplexed real-time and stored data

n A and B output sink capability of 48 mA, source

capability of 24 mA

n Guaranteed multiple output switching specifications

n Output switching specified for both 50 pF and 250 pF

loads

n Guaranteed simultaneous switching noise level and

dynamic threshold performance

n Guaranteed latchup protection

n High impedance glitch free bus loading during entire

power up and power down cycle

n Nondestructive hot insertion capability

n Standard Microcircuit Drawing (SMD) 5962-9457701

Ordering Code

Military

Package Number

Package Description

54ABT646J-QML

J24A

24-Lead Ceramic Dual-In-Line

54ABT646W-QML

W24C

24-Lead Cerpack

54ABT646E-QML

E28A

28-Lead Ceramic Leadless Chip Carrier, Type C

July 1998

© 1998 National Semiconductor Corporation

DS100209

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