C164SL datasheet(11/79 Pages) INFINEON

11 / 79 page

C164CI/SI

C164CL/SL

Data Sheet

V2.0, 2001-05

EA/

VPP 28

External Access Enable pin.

A low level at this pin during and after Reset forces the

C164CI to latch the configuration from PORT0 and pin RD,

and to begin instruction execution out of external memory.

A high level forces the C164CI to latch the configuration

from pins RD and ALE, and to begin instruction execution out

of the internal program memory.

“ROMless” versions must have this pin tied to ‘0’.

Note: This pin also accepts the programming voltage for the

OTP derivatives.

PORT0

P0L.0-7

P0H.0-7

29-

37-39,

42-46

PORT0 consists of the two 8-bit bidirectional I/O ports P0L

and P0H. It is bit-wise programmable for input or output via

direction bits. For a pin configured as input, the output driver

is put into high-impedance state.

In case of an external bus configuration, PORT0 serves as

the address (A) and address/data (AD) bus in multiplexed

bus modes and as the data (D) bus in demultiplexed bus

modes.

Demultiplexed bus modes:

Data Path Width:

8-bit

16-bit

P0L.0 – P0L.7:

D0 – D7

P0H.0 – P0H.7:

I/O

D8 – D15

Multiplexed bus modes:

Data Path Width:

8-bit

16-bit

P0L.0 – P0L.7:

AD0 – AD7

P0H.0 – P0H.7:

A8 – A15

AD8 – AD15

Table 2

Pin Definitions and Functions (cont’d)

Symbol Pin

No.

Input

Outp.

Function

C164SL Datasheet(PDF) 11 Page - Infineon Technologies AG

C164SL Datasheet(HTML) 11 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79

Datasheet Descarga

Enlace URL