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C868 Datasheet(PDF) 21 Page - Infineon Technologies AG |
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C868 Datasheet(HTML) 21 Page - Infineon Technologies AG |
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21 / 82 page ![]() C868 Data Sheet 21 V 1.0, 2003-05 Clock system The C868 clock system consist of the on-chip oscillator, PLL and multiplexer stage. The programmable Slow Down Divider (SDD) divides the PLL output clock frequency by a factor of 1...32 which is specified via CMCON.REL. The system clock is switched from the PLL output to the output from the SDD when slowdown mode is selected. Figure 11 Block Diagram of the Clock Generation On-Chip Osc clkin clkout f OSC XTAL1 XTAL2 PLL SDD MUX system clock ( fSYS) f PLL |
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