XIO2001IPNP datasheet(31/141 Pages) TI1

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XIO2001

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SCPS212I – MAY 2009 – REVISED JANUARY 2016

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8.3.3.1 Classic PCI Arbiter

The classic PCI arbiter is configured through the classic PCI configuration space at offset DCh. Table 5 identifies

and describes the registers associated with classic PCI arbitration mode.

Table 5. Classic PCI Arbiter Registers

PCI OFFSET

DESCRIPTION

Classic PCI configuration

Arbiter control

(see Arbiter Control

Contains a two-tier priority scheme for the bridge and six PCI bus devices. The

bridge defaults to the high priority tier. The six PCI bus devices default to the low

priority tier. A bus parking control bit (bit 7, PARK) is provided.

Classic PCI configuration

Arbiter request mask

(see Arbiter Request

Mask Register)

Six mask bits provide individual control to block each PCI Bus REQ input. Bit 7

(ARB_TIMEOUT) in the arbiter request mask register enables generating timeout

status if a PCI device does not respond within 16 PCI bus clocks. Bit 6

(AUTO_MASK) in the arbiter request mask register automatically masks a PCI bus

REQ if the device does not respond after GNT is issued. The AUTO_MASK bit is

cleared to disable any automatically generated mask.

Classic PCI configuration

Arbiter time-out status

(see Arbiter Time-Out

Status Register)

When bit 7 (ARB_TIMEOUT) in the arbiter request mask register is asserted,

timeout status for each PCI bus device is reported in this register.

8.3.4 Configuration Register Translation

PCI Express configuration register transactions received by the bridge are decoded based on the transaction’s

destination ID. These configuration transactions can be broken into three subcategories: type 0 transactions, type

1 transactions that target the secondary bus, and type 1 transactions that target a downstream bus other than

the secondary bus.

PCI Express type 0 configuration register transactions always target the configuration space and are never

passed on to the secondary interface.

Type 1 configuration register transactions that target a device on the secondary bus are converted to type 0

configuration register transactions on the PCI bus. Figure 10 shows the address phase of a type 0 configuration

transaction on the PCI bus as defined by the PCI specification.

Figure 10. Type 0 Configuration Transaction Address Phase Encoding

In addition, the bridge converts the destination ID device number to one of the AD[31:16] lines as the IDSEL

signal. The implemented IDSEL signal mapping is shown in Table 6.

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