Logic Diagram

’F169

TLF9488 – 5

Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays

Mode Select Table

PE

CEP

CET

UD

Action on Rising

Clock Edge

L

X

X

X

H

L

L

H

Count Up (Increment)

H

L

L

L

Count Down (Decrement)

H

H

X

X

No Change (Hold)

H

X

H

X

No Change (Hold)

State Diagram

’F169

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