TLE6263 datasheet(13/40 Pages) INFINEON

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Final Datasheet TLE 6263

Version 2.08

2004-06-07

The transmission cycle begins when the TLE6263 is selected by the chip select not input

CSN (H to L). After the CSN input returns from L to H, the word that has been read in

becomes the new control word. The DO output switches to tri-state status at this point,

thereby releasing the DO bus circuit for other uses. For details of the SPI timing please

refer to figure 6 to 9.

Table 5, Diagnosis Data Protocol

Table 6, Diagnosis Data Protocol

RxD-only mode

Vbat-Stand-by mode

6.6

Window Watchdog, Reset

When the input voltage exceeds the reset threshold voltage the reset output RO is

switched HIGH after a delay time of typ. 8ms. This is necessary for a defined start of the

microcontroller when the application is switched on. As soon as an under-voltage

condition of the output voltage (VCC < VRT) appears, the reset output RO is switched

LOW again (power on and under-voltage reset). The LOW signal is guaranteed down to

an output voltage VQ ≥ 1V. Please refer to figure 13, Reset Timing Diagram.

In sleep operation mode, the watchdog circuit is automatically disabled.

Long Open Window

After the above described delayed reset (LOW to HIGH transition of RO) the window

watchdog circuit is started by opening a long open window of typ. 65ms. The long open

window allows the microcontroller to run his set-up and then to trigger the watchdog via

the SPI, refer to figure 11,Watchdog Timeout Definitions. Within the long open window

OBIT

CAN Failure 5(4) and 7

VCC Not-Fail

CAN Failure 6 (3)

VINT Not-Fail

CAN Failure 6a (3a)

WK1/2 Initialization Fail

CAN Failure 2(1) and 4(5)

Wake via CAN bus lines

CAN Failure 3(6)

WK2 voltage level

CAN Failure 1(2) and 3a(6a)

WK1 voltage level

Window Watchdog Reset

Temperature Prewarning

H= ON

L= OFF

()... values in brackets according to

ISO11898-3 see table 2

H= ON

L= OFF

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