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UT8SP2M48 Datasheet(PDF) 12 Page - Aeroflex Circuit Technology |
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UT8SP2M48 Datasheet(HTML) 12 Page - Aeroflex Circuit Technology |
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12 / 23 page  12 36-00-01-001 Ver. 1.1.0 Aeroflex Microelectronics Solutions - HiRel AC CHARACTERISTICS (Pre and Post-Radiation)* (VDD= 2.3V to VDDQ, VDDQ = 2.3 to 3.6V; Unless otherwise noted, Tc is per the temperature range ordered.)1 PARAMETER DESCRIPTION MIN MAX UNIT tPowerup2 VDD to first valid command (READ or WRITE) 100 ms Clock tCYC Clock (CLK) cycle time 7.5 25.0 ns tCH CLK HIGH time 0.4 * tCYC 0.6 * tCYC ns tCL CLK LOW time 0.4 * tCYC 0.6 * tCYC ns tr, tf2 Input clock rise/fall time (10-90%) 2.25 V/ns tclkPJ3,5 Input clock period jitter -100 100 ps tclkCCJ3,5 Input clock cycle to cycle jitter 150 ps Setup Times tAS Address setup time prior to CLK 2.5 ns tDS Data setup time prior to CLK 1.5 ns tCENS Clock enable setup (CEN) time prior to CLK 3 ns tWES Write enable (WE) setup time prior to CLK 3 ns tBWES Byte Write enable (BWE[5:0]) setup time prior to CLK 3 ns tADVLDS Advance load (ADV_LD) setup time prior to CLK 2.5 ns tCSS Chip select (CSx) setup time prior to CLK 3 ns Hold Times tAH Address hold time after CLK 1.2 ns tDH Data hold time after CLK 1.4 ns tCENH CEN hold time after CLK 1.2 ns tWEH WE hold time after CLK 1.5 ns tBWEH Byte Write enable (BWE[5:0]) hold time after CLK 1.5 ns tADVLDH ADV_LD hold time after CLK 0.9 ns tCSH CSx hold time after CLK 1.8 ns Output Times tCQV4 Data valid after rising CLK 7 ns tOEQV4 Output enable (OE) active to data valid 4.0 ns tCQOH Data output hold time after rising CLK 2.0 ns tCQZ5 Rising CLK to output three-state time 5.0 ns tCQX5 Rising CLK to output enable time 1.3 ns |
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