Silicon Image, Inc.

Silicon Image, Inc.

14

Subject to Change without Notice

Dual Link Mode Operation

SiI161A operates up to the full DVI Single Link bandwidth of 165MHz. In Dual Link applications, two SiI161A chips

can be used to support pixel clock speeds up to 330MHz. These applications will only support panels with 48-bit, 2-

pixel per clock interfaces. See Figure 9 for connection details.

In Single Link mode, the transmitter system does not send any Data over the second link connected to the Slave

receiver. Therefore, the Slave receiver is not active and its outputs are tri-stated. All the Data, both EVEN and ODD

pixels, are sent over the link connected to the Master receiver. Therefore all the Data, both EVEN and ODD pixels,

for the panel is output by the Master receiver, which operates in 48-bit, 2-pixels per clock interface mode.

In Dual Link mode, the transmitter system sends EVEN Data over the link connected to the Master receiver and the

ODD Data over the link connected to the Slave receiver. Therefore, the EVEN Data for the panel is output by the

Master receiver and the ODD Data is output by the Slave receiver. The Master receiver’s ODD Data bus is tri-stated

to allow the Slave receiver’s EVEN Data bus to output the ODD Data for the panel.

PDO

ODCK

HSYNC

VSYNC

DO[23:0]

DE[23:0]

Rx(+/-)[3:1]

RxC(+/-)

PDO

ODCK

HSYNC

VSYNC

DO[23:0]

DE[23:0]

Rx(+/-)[3:1]

RxC(+/-)

NC

NC

NC

NC

PDO

ODCK

HSYNC

VSYNC

DE

DE[23:0]

DO[23:0]

PANEL

SCDT

TxC(+/-)

Tx1(+/-)[3:1]

Tx2(+/-)[3:1]

SYSTEM

Master

Slave

SiI161A

SiI161A

Figure 9: SiI161A Dual Link Block Diagram

Configuration:

Master –

The Master receiver will automatically configure to either Single or Dual Link operation (two or one pixel per

clock mode, respectively) depending on the transmitter system output. This is accomplished by connecting the

SCDT output pin of the Slave to the S_D pin on the Master. When the transmitter sends data on the second

link, the SCDT output of the slave (and the S_D pin on the Master) becomes high, setting to Dual Link (one-pixel

per clock) mode. If there is no data on the second link, the SCDT output of the Slave (and the S_D pin on the

Master) becomes LOW, and the Master receiver is in Single Link (two-pixels per clock) mode.