CD4538BC datasheet(5/10 Pages) NSC

5 / 10 page

Theory of Operation

TLF6000 – 4

FIGURE 2

Trigger Operation

The block diagram of the CD4538B is shown in

Figure 1

with circuit operation following

As shown in

Figures 1 and 2 before an input trigger occurs

the monostable is in the quiescent state with the Q output

low and the timing capacitor CX completely charged to

VDD When the trigger input A goes from VSS to VDD (while

inputs B and CD are held to VDD) a valid trigger is recog-

nized which turns on comparator C1 and N-Channel tran-

sistor N1 j At the same time the output latch is set With

transistor N1 on the capacitor CX rapidly discharges toward

VSS until VREF1 is reached At this point the output of com-

parator C1 changes state and transistor N1 turns off Com-

parator C1 then turns off while at the same time comparator

C2 turns on With transistor N1 off the capacitor CX begins

to charge through the timing resistor RX toward VDD When

the voltage across CX equals VREF2 comparator C2 chang-

es state causing the output latch to reset (Q goes low) while

at the same time disabling comparator C2 This ends the

timing cycle with the monostable in the quiescent state

waiting for the next trigger

A valid trigger is also recognized when trigger input B goes

from VDD to VSS (while input A is at VSS and input CD is at

VDD)k

It should be noted that in the quiescent state CX is fully

charged to VDD causing the current through resistor RX to

be zero Both comparators are ‘‘off’’ with the total device

current due only to reverse junction leakages An added

feature of the CD4538B is that the output latch is set

via the input trigger without regard to the capacitor voltage

Thus propagation delay from trigger to Q is independent of

the value of CX RX or the duty cycle of the input waveform

Retrigger Operation

The CD4538B is retriggered if a valid trigger occurs l fol-

lowed by another valid trigger m before the Q output has

returned to the quiescent (zero) state Any retrigger after

the timing node voltage at pin 2 or 14 has begun to rise from

VREF1 but has not yet reached VREF2 will cause an in-

crease in output pulse width T When a valid retrigger is

initiated m the voltage at T2 will again drop to VREF1 before

progressing along the RC charging curve toward VDD The

Q output will remain high until time T after the last valid

retrigger

Reset Operation

The CD4538B may be reset during the generation of the

output pulse In the reset mode of operation an input pulse

on CD sets the reset latch and causes the capacitor to be

fast charged to VDD by turning on transistor Q1n When

the voltage on the capacitor reaches VREF2 the reset latch

will clear and then be ready to accept another pulse If the

CD input is held low any trigger inputs that occur will be

inhibited and the Q and Q outputs of the output latch will not

change Since the Q output is reset when an input low level

is detected on the CD input the output pulse T can be made

significantly shorter than the minimum pulse width specifica-

tion

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