LP5520 datasheet(37/46 Pages) TI1

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LP5520

www.ti.com

SNVS440B – MAY 2007 – REVISED MARCH 2016

Product Folder Links: LP5520

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9 Power Supply Recommendations

The device is designed to operate with an input voltage supply range from 2.9 V to 5.5 V. In typical application

this is from single Li-ion battery cell. This input supply must be well regulated and able to withstand maximum

input current and maintain stable voltage without voltage drop even at load transition condition (start-up or rapid

brightness change). The resistance of the input supply rail must be low enough that the input current transient

does not cause a drop below the 2.9-V level in the LP5520 supply voltage.

10 Layout

10.1 Layout Guidelines

Figure 36 shows a layout recommendation for the LP5520 used to demonstrate the principles of good layout.

This layout can be adapted to the actual application layout if or where possible. It is important that all boost

components are close to the chip, and the high current traces must be wide enough. By placing boost

components on one side of the chip it is easy to keep the ground plane intact below the high current paths. This

way other chip pins can be routed more easily without splitting the ground plane. Bypass VLDO capacitor must

as close as possible to the device.

Here are main points to help with the PCB layout work:

•

Current loops need to be minimized:

–

For low frequency the minimal current loop can be achieved by placing the boost components as close to

the SW and GND_SW pins as possible. Input and output capacitor grounds must be close to each other to

minimize current loop size.

–

Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact

under the current traces. High-frequency return currents try to find route with minimum impedance, which

is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when

return current flows just under the positive current route in the ground plane, if the ground plane is intact

under the route.

•

GND plane must be intact under the high current boost traces to provide the shortest possible return path and

smallest possible current loops for high frequencies.

•

Current loops when the boost switch is conducting and not conducting must be on the same direction in

optimal case.

•

Inductor must be placed so that the current flows in the same direction as in the current loops. Rotating

inductor 180° changes current direction.

•

Use separate power and noise-free grounds or ground areas. Power ground is used for boost converter

return current and noise-free ground for more sensitive signals, like LDO bypass capacitor grounding as well

as grounding the GNDA pin of the device itself.

•

Boost output feedback voltage to LEDs must be taken out after the output capacitors, not straight from the

diode cathode.

•

Place LDO 1-µF bypass capacitor as close to the LDO pin as possible.

•

Input and output capacitors need strong grounding (wide traces, many vias to GND plane).

•

If two output capacitors are used they need symmetrical layout to get both capacitors working ideally.

•

Output ceramic capacitors have DC-bias effect. If the output capacitance is too low, it can cause boost to

become unstable on some loads; this increases EMI. DC bias characteristics should be obtained from the

component manufacturer; DC bias is not taken into account on component tolerance. TI recommends

X5R/X7R capacitors.

LP5520 Datasheet(PDF) 37 Page - Texas Instruments

LP5520 Datasheet(HTML) 37 Page - Texas Instruments

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