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PI6C49016 Datasheet(PDF) 2 Page - Pericom Semiconductor Corporation |
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PI6C49016 Datasheet(HTML) 2 Page - Pericom Semiconductor Corporation |
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2 / 16 page ![]() 2 www.pericom.com PI6C49016 Rev. B 06/25/13 PI6C49016 Low Power Networking Clock Generator Pin Description Pin# Pin Name Pin Type Pin Description 1 VDD Power 3.3V Supply Pin 2 GND Power Ground 3 VDD Power 3.3V Supply Pin 4 NC - - 5 NC - - 6 GND Power Ground 7 VDD Power 3.3V Supply Pin 8 SCLK Input SMBus clock input 9 SDATA I/O SMBus data input 10 GND Power Ground 11 80M Output 80 MHz LVCMOS output. Tri-state with weak pull- down when disabled 12 VDD Power 3.3V Supply Pin 13 VDD Power 3.3V Supply Pin 14 GNDX Power Ground 15 PD_RESET Input Global reset input powers down PLLs plus tri-states outputs and sets the I2C tables to their default state when pulled low. Controlled by external POR Pin List Power Grouping Pins Group Description 1, 3, 7, 30 Power for PCIe clocks 12 Power for 80 MHz PLL and output 13, 22, 28 Power for 60/66 MHz PLL and outputs 18 Power for crystal oscillator 19 Output Power for 125 MHz 25 Power for 125 MHz PLL 35, 37 Digital power 1 GND 40-pin QFN VDD GND GND VDD GND VDD GND 11 21 31 NC NC VDD SCLK SDATA GND 66.66M NC VDD GND VDD VDD 13-0102 |
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