PI6C49021 datasheet(2/15 Pages) PERICOM

2 / 15 page

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P-0.1

02/27/13

PI6C49021

Low Power High Integration Clock Generator

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Pin Configuration

Pin#

Pin Name

Pin Type

Pin Description

1, 6, 11, 24, 30, 34, 35

GND

Power

Ground

Do not Connect

PCIE2

Output

100MHz HCSL output

PCIE2#

Output

100MHz HCSL output

5, 7, 8, 12, 21, 26, 28,

31, 32, 36, 39, 42, 43,

VDD

Power

Power supply

SE_50M0

Output

50MHz LVCMOS output

SE_50M1

Output

50MHz LVCMOS output

SE_25M0

Output

25MHz LVCMOS output

SE_25M1

Output

25MHz LVCMOS output

SE_25M2

Output

25MHz LVCMOS output

SDATA

I/O

I2C compatible data

SCLK

Input

I2C compatible clock

Do not Connect (can be used as RESET# pin, global

reset input powers down PLLs plus tri-states outputs

and sets the I2C tables to their default state when pulled

low.)

Input

Crystal input. Connect to 25MHz

Fundamental mode crystal or clock.

Output

Crystal output. Connect to 25MHz

Fundamental mode crystal. Float for clock input.

Pin Description

GND

PCIE2

PCIE2#

VDD

GND

VDD

SE_50M0

SE_50M1

GND

VDD

GND

VDD

GND

SE_66M1

VDD

SE_66M0

SE_125M

14 15 16

17 18 19 20 21 22 23 24

48 47 46 45

44 43 42 41 40 39 38 37

VDD

SE_24M

VDD

Pins

Group Description

Power for 66.667MHz PLL

Power for 24MHz PLL

Power for 125M/50MHz PLL

Power for 100MHz PCIe PLL

Power for 50MHz outputs

Power for 25MHz LVCMOS outputs

Power for crystal oscillator

Power for 24MHz output

Power for 66.667MHz outputs

Power for 125MHz output

39, 42

Power for 25MHz differential outputs

43, 46

Power for PCIe clock outputs

13-0015

PI6C49021 Datasheet(PDF) 2 Page - Pericom Semiconductor Corporation

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