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ADC08161CIWM Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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ADC08161CIWM Datasheet(HTML) 2 Page - National Semiconductor (TI) |
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2 / 15 page  Connection Diagram Ordering Information Industrial (−40˚C ≤ T A ≤ 85˚C) Package ADC08161CIWM M20B Pin Description V IN This is the analog input. The input range is GND–50 mV ≤ V INPUT ≤ V + +50mV. DB0–DB7 TRI-STATE data outputs — bit 0 (LSB) through bit 7 (MSB). WR /RDY WR-RD Mode (Logic high applied to MODE pin) WR: With CS low, the conversion is started on the rising edge of WR. The digi- tal result will be strobed into the output latch at the end of conversion ( Figures 2, 3, 4). RD Mode (Logic low applied to MODE pin) RDY: This is an open drain output (no in- ternal pull-up device). RDY will go low af- ter the falling edge of CS and returns high at the end of conversion. MODE Mode: Mode (RD or WR-RD ) selection input– This pin is pulled to a logic low through an internal 50 µA current sink when left unconnected. RD Mode is selected if the MODE pin is left unconnected or externally forced low. A complete conversion is accomplished by pulling RD low until output data appears. WR-RD Mode is selected when a high is applied to the MODE pin. A conversion starts with the WR signal’s rising edge and then using RD to access the data. RD WR-RD Mode (logic high on the MODE pin) This is the active low Read input. With a logic low applied to the CS pin, the TRI-STATE data outputs (DB0–DB7) will be activated when RD goes low ( Figures 2, 3, 4). RD Mode (logic low on the MODE pin) With CS low, a conversion starts on the falling edge of RD. Output data appears on DB0–DB7 at the end of conversion ( Figures 1, 5). INT This is an active low output that indicates that a conversion is complete and the data is in the output latch. INT is reset by the rising edge of RD. GND This is the power supply ground pin. The ground pin should be connected to a “clean” ground reference point. V REF−,VREF+ These are the reference voltage inputs. They may be placed at any voltage be- tween GND − 50 mV and V + +50mV, but V REF+ must be greater than VREF−. Ideally, an input voltage equal to V REF− produces an output code of 0, and an input voltage greater than V REF+ − 1.5 LSB produces an output code of 255. For the ADC08161 an input voltage that exceeds V + by more than 100 mV or is be- low GND by more than 100 mV will create conversion errors. CS This is the active low Chip Select input. A logic low signal applied to this input pin en- ables the RD and WR inputs. Internally, the CS signal is ORed with RD and WR signals. OFL Overflow Output. If the analog input is higher than V REF+, OFL will be low at the end of conversion. It can be used when cascading two ADC08161s to achieve higher resolution (9 bits). This output is al- ways active and does not go into TRI-STATE as DB0–DB7 do. When OFL is set, all data outputs remain high when the ADC08061’s output data is read. V + Positive power supply voltage input. Nomi- nal operating supply voltage is +5V. The supply pin should be bypassed with a 10 µF bead tantalum in parallel with a 0.1 ceramic capacitor. Lead length should be as short as possible. V REFOUT The internal bandgap reference’s 2.5V output is available on this pin. Use a 220 µF bypass capacitor between this pin and analog ground. Wide-Body Small-Outline Package DS011149-14 See NS Package Number M20B www.national.com 2 |
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