M08045 datasheet(8/49 Pages) MA-COM

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Electrical Characteristics

M08035, M08045 Data Sheet V1

MACOM

™

080x5-DSH-001

Table 1-8.

Reclocker Specifications (M08045)

Symbol

Parameter

Conditions

Note

Minimum

Typical

Maximum

Unit

tLOCK

Lock time (asynchronous)

Automatic rate detection enabled

—

FLBW, PEAK

Loop bandwidth peaking

—

0.1

—

FLBW

Loop bandwidth

(nominal setting)

3G operation (2.97 Gbps)

—

1.7

—

MHz

HD operation (1.485 Gbps)

—

0.85

—

SD operation (270 Mbps)

—

0.17

—

JTOL

Input jitter tolerance

3G, HD, and SD operation

> 0.6

—

UI p-p

JGEN

Total Output jitter

3G operation (2.97 Gbps)

2, 3

—

0.07

0.11

UI p-p

HD operation (1.485 Gbps)

2, 3

—

0.04

0.06

SD operation (270 Mbps)

2, 3

—

0.02

0.05

NOTE:

0.2 UI input jitter applied at SDI input.

Measured with PRBS210-1.

Input jitter = 20 ps p-p.

Table 1-9.

XTALP/N and Reference Clock Electrical Specifications

Symbol

Parameter

Note

Minimum

Typical

Maximum

Unit

FREF

XTAL/Ref clock frequency

—

MHz

FREF, ppm

XTAL/Ref clock frequency accuracy

—

-100

100

ppm

CLOAD

XTAL load capacitance

—

CLOCKJITT

Jitter (RMS)

2, 4

—

CLOCKDCT

Reference clock duty cycle

tolerance

240

—

RIN

Input impedance

2, 5

200

750

1500

VIN

Input amplitude

0.8

—

1.2

tR/tF

Rise/Fall time

2, 6

—

NOTE:

This capacitance is supplied internally (no external cap is required).

When using an external reference clock source, this should be AC coupled through a 0.1 µF capacitor.

When using an external clock a small increase in jitter may be seen. For best performance a crystal is recommended.

Jitter bandwidth is from 12 kHz to 20 MHz.

Measured with TDR module.

10% to 90% rise and fall times.

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