CGS701AV datasheet(2/10 Pages) NSC

No. de pieza	CGS701AV

Descripción Electrónicos	Commercial, Industrial Low Skew PLL 1 to 8 CMOS Clock Driver

PDF	10 Pages

Scroll/Zoom	100%

Fabricante Electrónico	NSC [National Semiconductor (TI)]

Página de inicio	http://www.national.com

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2 / 10 page

CGS701A

General Description (Continued)

CLK1SEL pin changes the output frequency of the

CLK1

0 thru CLK1

5 outputs During normal operation

when CLK1SEL pin is high these outputs are at the same

frequency as the input crystal oscillator while CLK2 and

CLK4 outputs are at twice and four times the input frequen-

cy respectively

Once CLK1SEL pin is set to a low logic level the CLK1

outputs will be at twice the input frequency the same as the

CLK2 output with CLK4 output still being at four times the

input frequency

In addition another pin is added for increasing the test ca-

pability SKWSEL pin allows testing of the counter’s output

and skew of the output drivers by bypassing the VCO In this

test mode CLK4 frequency is the same as SKWTST input

frequency while CLK2 is 12 and CLK1 frequencies are 14

respectively (refer to the Truth Table) In addition CLK1SEL

functionality is also true under this test condition

Block Diagram

TLF11920 – 2

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CGS701AV Datasheet(PDF) 2 Page - National Semiconductor (TI)