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CLC418 Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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CLC418 Datasheet(HTML) 7 Page - National Semiconductor (TI) |
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7 / 12 page ![]() 7 http://www.national.com following equation: SR > 5 • f • V peak where Vpeak is the peak output sinusoidal voltage. The slew rate of the CLC418 in inverting gains is always higher than in non-inverting gains. AC Design (linear phase/constant group delay) The recommended value of Rf produces minimal peaking and a reasonably linear phase response. To improve phase linearity when |Av| < 6, increase Rf approximately 50% over its recommended value. Some adjustment of Rf may be needed to achieve phase linearity for your application. See the AC Design (small signal band- width) sub-section for other effects of changing Rf. Propagation delay is approximately equal to group delay. Group delay is related to phase by this equation: where φ(f) is the phase in degrees. Linear phase implies constant group delay. The technique for achieving linear phase also produces a constant group delay. AC Design (peaking) Peaking is sometimes observed with the recommended Rf. If a small increase in Rf does not solve the problem, then investigate the possible causes and remedies listed below: s Capacitance across Rf s Do not place a capacitor across Rf s Use a resistor with low parasitic capacitance for Rf s A capacitive load s Use a series resistor between the output and a capacitive load (see the Settling Time versus CL plot) s Long traces and/or lead lengths between Rf and the CLC418 s Keep these traces as short as possible For non-inverting and transimpedance gain configurations: s Extra capacitance between the inverting pin and ground (Cg) s See the Printed Circuit Board Layout sub-section below for suggestions on reducing Cg s Increase Rf if peaking is still observed after reducing Cg For inverting gain configurations: s Inadequate ground plane at the non-inverting pin and/or long traces between non-inverting pin and ground s Place a 50 to 200 Ω resistor between the non-inverting pin and ground (see Rt in Figure 2) AC Design (crosstalk) Crosstalk performance depends on the layout. Three layout techniques that can reduce crosstalk are: s Provide short symmetrical ground return paths for: s the inputs s the supply bypass capacitors s the load s Provide a short, grounded guard trace that: s goes underneath the package s is 0.1” (3mm) from the package pins s is on top and bottom of the printed circuit board with connecting vias s Try different bypass capacitors to reduce high frequency crosstalk The CLC418’s evaluation board was used to produce the Input-Referred Crosstalk plot. Capacitive Loads Capacitive loads, such as found in A/D converters, require a series resistor (Rs) in the output to improve settling performance. The Settling Time vs. Capacitive Load plot in the Typical Performance Characteristics section provides the information for selecting this resistor. Using a resistor in series with a reactive load will also reduce the load’s effect on amplifier loop dynamics. For instance, driving coaxial cables without an output series resistor may cause peaking or oscillation. Transmission Line Matching One method for matching the characteristic impedance of a transmission line is to place the appropriate resistor at the input or output of the amplifier. Figure 6 shows the typical circuit configurations for matching transmission lines. Figure 6: Transmission Line Matching In non-inverting gain applications, Rg is connected directly to ground. The resistors R1, R2, R6, and R7 are equal to the characteristic impedance, Zo, of the transmission line or cable. Use R3 to isolate the amplifier from reactive loading caused by the transmis- sion line, or by parasitics. In inverting gain applications, R3 is connected directly to ground. The resistors R4, R6, and R7 are equal to Zo. The parallel combination of R5 and Rg is also equal to Zo. The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C6 to match the output transmission line over a greater frequency range. It compensates for the increase of the op amps output impedance with frequency. τ φ φ gd d d f 1 360 f f 1 360 f f ( ) = − ° ⋅ ( ) ≈ − ° ⋅ ( ) ∆ ∆ + - 418 Fig6 R3 Z0 R6 Vo Z0 R1 R2 + - Rg Z0 R4 R5 V1 V2 +- Rf C6 R7 1/2 CLC418 |
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