TMC424 Datasheet – (V1.04 / 2015-JUL-01)

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Copyright © 2011 TRINAMIC Motion Control GmbH & Co. KG

7.3 Timer Logic Step Pulse Length and Delay

To parameterize the step length and delay the next datagram is to be used:

Bit

Write Step Pulse Length / Delay

31…25

“0000111” Register Address

24

‘1’

23…16

Step Pulse Length (default value = 48

15…6

Step Pulse Delay after Direction Change (default value = 160

5…0

Reserved

Table 8: SPI Datagram Step-/Dir logic

7.4 Control Register and Interrupt Control

This datagram configures the interrupt control of the TMC424. When enabled, the N channel pulse of

all encoders is fed to the NINT pin.

Bit

Control Register

31…25

“0001000” Register Address

24

‘1’

23

Set Common Hold for Encoder Hold Registers

0 = no hold (default)

1 = freeze encoder hold registers

22

Encoder Interrupt Enable, if Null signal

0 = interrupt disable (default)

1 = interrupt enable

21

Clear Interrupt Flags

0 = no clear (default)

1= clear flags

20…0

Reserved

Table 9: SPI Datagram Control Register

7.5 N-Channel Read Back

This datagram returns the state of the three N-Channel inputs ENCx_N after the possible inverting

controlled by ENC_INV. The three inputs are sampled after transmission of the R/W bit. The three bits

are repeated in the datagram for compatibility reasons as if the N-signals were connected to the

SW_ROW_PIN(0..2) inputs of a TMC423.

Bit

Channel

31…25

“0001001” Register Address

24

‘0’

23…21, 17…15,

11…9, 5…3

“000”

20, 14, 8, 2

ENC3_N when ENC_INV = 0, not ENC3_N when ENC_INV = 1

19, 13, 7, 1

ENC2_N when ENC_INV = 0, not ENC2_N when ENC_INV = 1

18, 12, 6, 0

ENC1_N when ENC_INV = 0, not ENC1_N when ENC_INV = 1

Table 10: N-Channel Read Back Register