COP688GD datasheet(37/42 Pages) NSC

37 / 42 page

Instruction Execution Time

Most instructions are single byte (with immediate addressing

mode instructions taking two bytes).

Most single byte instructions take one cycle time to execute.

See the BYTES and CYCLES per INSTRUCTION table for

details.

Bytes and Cycles per Instruction

The following table shows the number of bytes and cycles for

each instruction in the format of byte/cycle.

Arithmetic and Logic Instructions

[B]

Direct

Immed.

ADD

1/1

3/4

2/2

ADC

1/1

3/4

2/2

SUBC

1/1

3/4

2/2

AND

1/1

3/4

2/2

1/1

3/4

2/2

XOR

1/1

3/4

2/2

IFEQ

1/1

3/4

2/2

IFNE

1/1

3/4

2/2

IFGT

1/1

3/4

2/2

IFBNE

1/1

DRSZ

1/3

SBIT

1/1

3/4

RBIT

1/1

3/4

IFBIT

1/1

3/4

RPND

1/1

Instructions Using A & C

CLRA

1/1

INCA

1/1

DECA

1/1

LAID

1/3

DCOR

1/1

RRCA

1/1

RLCA

1/1

SWAPA

1/1

IFC

1/1

IFNC

1/1

PUSHA

1/3

POPA

1/3

ANDSZ

2/2

Transfer of Control Instructions

JMPL

3/4

JMP

2/3

1/3

JSRL

3/5

JSR

2/5

JID

1/3

VIS

1/5

RET

1/5

RETSK

1/5

RETI

1/5

INTR

1/7

NOP

1/1

Memory Transfer Instructions

Direct

Immed.

Indirect

Auto Incr. & Decr.

[B]

[X]

[B+, B−]

[X+, X−]

X A, (Note *NO

TARGET FOR

FNXref

NS7829*)

1/1

1/3

2/3

1/2

1/3

LD A, (Note

*NO TARGET

FOR FNXref

NS7829*)

1/1

1/3

2/3

2/2

1/2

1/3

LD B, Imm

1/1

(IF B < 16)

LD B, Imm

2/2

(IF B > 15)

LD Mem, Imm

2/2

3/3

2/2

LD Reg, Imm

2/3

IFEQ MD, Imm

3/3

Note 33:

> Memory location addressed by B or X or directly.

COP688GD Datasheet(PDF) 37 Page - National Semiconductor (TI)

COP688GD Datasheet(HTML) 37 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Descarga

Enlace URL