PCI9060ES datasheet(59/192 Pages) ETC

59 / 192 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 50

Version 1.02

4.2 REGISTER ADDRESS MAPPING

4.2.1 PCI Configuration Registers

Table 4-5. PCI Configuration Registers

To ensure software compatibility with other versions of the PCI 9080 family and to

ensure compatibility with future enhancements,

write a zero to all unused bits.

PCI CFG

Address

Local

Access

(Offset

from Chip

Select

Address)

PCI/Local

Writable

Serial

EEPROM

Writable

00h

Device ID

Vendor ID

Local

04h

Status

Command

08h

Class Code

Revision ID

Local

0Ch

BIST

Header Type

PCI Latency Timer

Cache Line Size

Y [15:0],

Local

10h

PCI Base Address 0 for Memory Mapped Configuration Registers (PCIBAR0)

14h

PCI Base Address 1 for I/O Mapped Configuration Registers (PCIBAR1)

18h

PCI Base Address 2 for Local Address Space 0 (PCIBAR2)

1Ch

PCI Base Address 3 for Local Address Space 1 (PCIBAR3)

20h

Unused Base Address (PCIBAR4)

24h

Unused Base Address (PCIBAR5)

28h

Cardbus CIS Pointer (Not Supported)

2Ch

Subsystem ID

Subsystem Vendor ID

Local

30h

PCI Base Address for Local Expansion ROM

34h

Reserved

38h

Reserved

3Ch

Max_Lat

Min_Gnt

Interrupt Pin

Interrupt Line

Y [7:0],

Local

Note:

Refer to the PCI 2.1 spec for definitions of these registers.

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