1

0

A2

A1 A0

0

0

0

0

A2

A1

A0

0

1

S0

A

A

A

COMMAND BYTE

acknowledge

from slave

R/W

acknowledge

from slave

A

P

NA

acknowledge

from slave

acknowledge

from master

S

DATA

DATA

R/W

first byte

at this moment master-transmitter

becomes master-receiver and

slave-receiver becomes

slave-transmitter

last byte

SU01463

no acknowledge

from master

1

slave address

data from upper

or lower byte of

register

data from lower

or upper byte

of register

slave address

MSB

LSB

MSB

LSB

NOTE: Transfer can be stopped at any time by a STOP condition.

Figure 8.

READ from register

1

23456789

S

0

100

A2

A1

A0

1

A

7

654

321

0

A

I0.x

765

4

3

2

1

0

A

I1.x

7

654

321

0

A

I0.x

7

6

54

32

1

0

1

I1.x

P

R/W

ACKNOWLEDGE

FROM SLAVE

SCL

SDA

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

NON ACKNOWLEDGE

FROM MASTER

READ FROM PORT 0

DATA INTO PORT 0

READ FROM PORT 1

DATA INTO PORT 1

INT

SU01464

NOTES: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).

It is assumed that the command byte has previously been set to 00 (read input port port register).

Figure 9.

READ input port register — scenario 1