AD5347 datasheet(20/24 Pages) AD

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AD5346/AD5347/AD5348

Rev. 0 | Page 20 of 24

DECODING MULTIPLE AD5346/AD5347/AD5348s

The CS pin on these devices can be used in applications to

decode a number of DACs. In this application, all DACs in the

system receive the same data and WR pulses, but only the CS to

one of the DACs will be active at any one time, so data will only

be written to the DAC whose CS is low.

The 74HC139 is used as a 2-line to 4-line decoder to address

any of the DACs in the system. To prevent timing errors from

occurring, the enable input should be brought to its inactive

state while the coded address inputs are changing state.

Figure 44 shows a diagram of a typical setup for decoding

multiple devices in a system. Once data has been written

sequentially to all DACs in a system, all the DACs can be

updated simultaneously using a common LDAC line. A com-

mon CLR line can also be used to reset all DAC outputs to 0 V.

ENABLE

CODED

ADDRESS

VDD

VCC

74HC139

DGND

1Y0

1Y1

1Y2

1Y3

LDAC

CLR

DATA

INPUTS

DATA

INPUTS

DATA

INPUTS

DATA

INPUTS

LD AC

CLR

LD AC

CLR

AD5346/AD5347

/AD5348

LD AC

CLR

LD AC

CLR

AD5346/AD5347

/AD5348

AD5346/AD5347

/AD5348

AD5346/AD5347

/AD5348

Figure 44. Decoding Multiple DAC Devices

AD5346/AD5347/AD5348 AS DIGITALLY

PROGRAMMABLE WINDOW DETECTORS

A digitally programmable upper/lower limit detector using two

of the DACs in the AD5346/AD5347/AD5348 is shown in

Figure 45. Any pair of DACs in the device may be used, but for

simplicity the description refers to DACs A and B.

The upper and lower limits for the test are loaded to DACs A

and B which, in turn, set the limits on the CMP04. If a signal at

the VIN input is not within the programmed window, an LED

indicates the fail condition.

GND

VREFAB

VDD

VIN

FAIL

PASS

Ω

PASS/

FAIL

1/6 74HC05

1/2

CMP04

VREF

0.1

µF

VOUTB

VOUTA

AD5346/AD5347/

AD5348

Figure 45. Programmable Window Detector

PROGRAMMABLE CURRENT SOURCE

Figure 46 shows the AD5346/AD5347/AD5348 used as the

control element of a programmable current source. In this

example, the full-scale current is set to 1 mA. The output

voltage from the DAC is applied across the current setting

resistor of 4.7 kΩ in series with the 470 Ω adjustment

potentiometer, which gives an adjustment of about ±5%.

Suitable transistors to place in the feedback loop of the ampli-

fier include the BC107 and the 2N3904, which enable the

current source to operate from a minimum VSOURCE of 6 V. The

operating range is determined by the operating characteristics

of the transistor. Suitable amplifiers include the AD820 and the

OP295, both having rail-to-rail operation on their outputs. The

current for any digital input code and resistor value can be

calculated as follows:

REF

)

(

where:

G is the gain of the buffer amplifier (1 or 2).

D is the digital input code.

N is the DAC resolution (8, 10, or 12 bits).

R is the sum of the resistor plus adjustment potentiometer in kΩ.

VDD = 5V

LOAD

VSOURCE

EXT

REF

GND

VOUT

4.7k

Ω

470

Ω

*ONLY ONE CHANNEL OF VREF AND VOUT SHOWN

0.1

µF

0.1

µF

VIN

GND

AD5346/AD5347/

AD5348

VDD

VREF*VOUT*

Figure 46. Programmable Current Source

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