EN

IN

Y:/1

Y:/2

Y:/4

High-Z

High-Z

High-Z

Undefined

Undefined

Undefined

Low

Low

Low

1 us

EN

IN

Y:/1

Y:/2

Y:/4

High-Z

High-Z

High-Z

Undefined

Undefined

Undefined

Low

Low

Low

1 us

Signal State After the Device is Enabled (IN = Low)

Signal State After the Device is Enabled (IN = High)

Undivided State is Valid After the First

Positive Transition of the Input Clock

CDCM1802

www.ti.com

SCAS759B – APRIL 2004 – REVISED NOVEMBER 2015

Figure 12. Waveforms

8.4.2.2 Enabling a Single Output Stage

If a single output stage becomes enabled:

•

Y0 will either be low or high (undefined).

•

Y0 will be the inverted signal of Y0.

With the first positive clock transition, the undivided output becomes the input clock state. If a divide mode is

used, the divided output states are equal to the actual internal divider. The internal divider does not get a reset

while enabling single output drivers.

Copyright © 2004–2015, Texas Instruments Incorporated

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