1

2

3

4

5

10

9

8

7

6

LM3205

Top View

PGND

PGND

SGND

VCON

FB

SW

PVin

PVin

VDD

EN

1

2

3

4

5

10

9

8

7

6

LM3205

Bottom View

PGND

PGND

SGND

VCON

FB

SW

PVin

PVin

VDD

EN

A1

B1

C1

A3

B3

C3

SW

A2

C2

EN

PGND

SGND

FB

A3

B3

C3

A1

B1

C1

A2

C2

SW

PGND

SGND

FB

EN

Top View

Bottom View

LM3205

SNVS388E – JULY 2005 – REVISED APRIL 2013

www.ti.com

CONNECTION DIAGRAMS

Figure 2. 8–Bump Thin DSBGA Package, Large Bump

NS Package Number YZR0008GNA

Figure 3. 10–Pin WSON

NS Package Number DSC0010A

PIN DESCRIPTIONS

Pin #

Name

Description

DSBGA

WSON

A1

8, 9

Power Supply Voltage Input to the internal PFET switch.

B1

7

Analog Supply Input.

C1

6

EN

Enable Input. Set this digital input high for normal operation. For shutdown, set low.

C2

4

C3

5

FB

Feedback Analog Input. Connect to the output at the output filter capacitor.

B3

3

SGND

Analog and Control Ground

A3

1, 2

PGND

Power Ground

A2

10

SW

Switch node connection to the internal PFET switch and NFET synchronous rectifier.

Connect to an inductor with a saturation current rating that exceeds the maximum Switch Peak

Current Limit specification of the LM3205.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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