DP8441VLJ-40 datasheet(2/46 Pages) NSC

2 / 46 page

DRAM

Maximum Clock

Package

Bus Width

Largest DRAM

Controller

Frequency

Type

Supporting

Possible

DP8440V-40

40 MHz

84-Pin PLCC

8 16 32

16 Mbits

DP8440VLJ-40

40 MHz

100-Pin PQFP

8 16 32

16 Mbits

DP8440VLJ-25

25 MHz

100-Pin PQFP

8 16 32

16 Mbits

DP8441VLJ-40

40 MHz

100-Pin PQFP

8 16 32 64

64 Mbits

DP8441VLJ-25

25 MHz

100-Pin PQFP

8 16 32 64

64 Mbits

Table of Contents

10 CONNECTION DIAGRAMS

20 FUNCTIONAL INTRODUCTION

30 SIGNAL DESCRIPTION

31 Address and Control Signals

32 DRAM Control Signals

33 Refresh Signals

34 Reset and Programming Signals

35 Clock Inputs

36 Power Signals and Capacitor Input

40 PROGRAMMING AND RESETTING

41 Reset

42 Programming Sequence

43 Programming Selection Bits

50 ACCESS MODES

51 Opening Access

52 Normal Mode

53 Page Mode

54 Burst Access

55 Inner Page Burst Access

60 REFRESH MODES

61 Auto-Internal Refresh

62 Externally Controlled Refresh

63 Error Scrubbing during Refresh

64 Extending Refresh

65 Refresh Types

70 WAIT SUPPORT

71 DTACK During Opening Access

72 DTACK During Page Access

73 DTACK During Burst Access

74 Next Address or Early DTACK Support

80 ABSOLUTE MAXIMUM RATINGS

90 DC ELECTRICAL CHARACTERISTICS

100 LOAD CAPACITANCE

110 AC TIMING PARAMETERS

120 AC TIMING WAVEFORMS

CLK and DECLK Timing

Refresh Timing

Refresh and Access Timing

Programming and Initialization Period Timing

Normal Mode Access Timing

Page Mode Access Timing

Burst Mode Access Timing

130 ERRATA

140 PHYSICAL DIMENSIONS

DP8441VLJ-40 Datasheet(PDF) 2 Page - National Semiconductor (TI)

DP8441VLJ-40 Datasheet(HTML) 2 Page - National Semiconductor (TI)

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