Circuit Description

STV7697B

8/18

All the data are kept memorized in the latch stage when the strobe input (STB) is pulled high.

The Blanking input (BLK) forces the power outputs to high level when pulled high with polarity input

(POL) at high level and forced to low level with POL at low level. The level of the power output is

inverted when the polarity command (POL) is pulled high.

Driver outputs can be simultaneously polarized at high or low level depending on the biasing of the

application.

clock periods.

Table 6: Power Output Truth Table

*

CLR

STB

BLK

POL

Driver

Output

Comments

X

X

X

H

H

All H

Forced to High

X

X

X

H

L

All L

Forced to Low

H

L

L

L

L

H

Copy Data

LL

LL

LL

Copy Data

H

L

L

L

H

L

Copy Inverted Data

L

L

L

L

H

H

Copy Inverted Data

X

X

H

L

L

Qn

Data Latched

X

X

H

L

H

Qn

Inverted Data Latched

X

H

LL

LL

All Low

XH

L

L

H

H

All High