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2015-07-0038

PT0535-4

8/18/15

7

PI4MSD5V9543B

2 Channel I2C bus switch

with Interrupt Logic and Reset

Figure 4:Device address

The PI4MSD5V9543B is an alternate address version, if needed for larger systems or to resolve address conflicts.

The data sheet will reference the PI4MSD5V9543A, but the PI4MSD5V9543B functions identically except for the

slave address.

Control register

Following the successful acknowledgement of the slave address, the bus master will send a byte to the

PI4MSD5V9543B, which will be stored in the control register. If multiple bytes are received by the PI4MSD5V9543B,

it will save the last byte received. This register can be written and read via the I2C-bus.

Figure 5: Control register

Control register definition

One or several SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This

register is written after the PI4MSD5V9543B has been addressed. The 2 LSBs of the control byte are used to

determine which channel is to be selected. When a channel is selected, the channel will become active after a STOP

condition has been placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the

channel is made active, so that no false conditions are generated at the time of connection.

Bits INT0, INT1, D6 and D7 are all writable, but will read the chip status. INT0 and INT1 indicate the state of the

corresponding interrupt input. D7 and D6 always read 0.

D7

D6

INT1

INT0

D3

B2

B1

B0

Command

X

X

X

X

X

X

X

0

channel 0 disabled

1

channel 0 enabled

X

X

X

X

X

X

0

X

channel 1 disabled

1

channel 1enabled

0

0

0

0

0

0

0

0

no channel selected;

power-up/reset default state

Control register: Write—channel selection; Read—channel status.

Remark: Channel 0 and channel 1 can be enabled at the same time. Care should be

taken not to exceed the maximum bus capacitance.