LP3913 datasheet(34/70 Pages) TI1

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ADR6

bit7

MSB

R/W

LSB

ADR5

bit6

ADR3

bit4

ADR2

bit3

ADR1

bit2

ADR1

bit1

ADR4

bit5

bit0

C SLAVE address (chip address)

I2C_SDA

S TART condition

STO

Pcondition

I2C_SCL

I2C_SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

LP3913

SNVS489I – NOVEMBER 2006 – REVISED SEPTEMBER 2013

www.ti.com

Figure 59. I2C Signals: Data Validity

I2C START and STOP Conditions

START and STOP bits classify the beginning and the end of the I2C session. The START condition is defined the

as the I2C_SDA signal transitioning from HIGH to LOW while SCL line is HIGH. The STOP condition is defined

as the SDA transitioning from LOW to HIGH while I2C_SCL is HIGH. The I2C master always generates START

and STOP bits. The I2C bus is considered to be busy after a START condition and free after a STOP condition.

During data transmission, I2C master can generate repeated START conditions. First START and repeated

START conditions are equivalent, function-wise.

Figure 60. START and STOP Conditions

Transferring Data

Every byte put on the I2C_SDA line must be eight bits long, with the most significant bit (MSB) being transferred

first. Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is

generated by the master. The transmitter releases the I2C_SDA line (HIGH) during the acknowledge clock pulse.

The receiver must pull down the I2C_SDA line during the 9th clock pulse, signifying acknowledgement. A receiver

which has been addressed must generate an acknowledgement (“ACK”) after each byte has been received.

After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W). For the eighth bit, a “0” indicates a WRITE and a “1” indicates a

READ. The second byte selects the register to which the data will be written. The third byte contains data that

will be written to the selected register.

LP3913 has a chip address of 60’h, which is set by a metal mask option.

Figure 61. I2C Chip Address

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