TNETV1002IDZHK datasheet(71/102 Pages) TI1

No. de pieza	TNETV1002IDZHK

Descripción Electrónicos	Fixed-Point Digital Signal Processor

PDF	102 Pages

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Fabricante Electrónico	TI1 [Texas Instruments]

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Electrical Specifications

June 2001 -- Revised December 2002

SPRS180C

6.8

Interrupt Timings

Table 6--13 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 6--12).

Table 6--13. Reset and Interrupt Timing Requirements

MIN

MAX

UNIT

tw(INTH)S

Pulse duration, DSP_INT0 high (synchronous)

2H+1

tw(INTL)S

Pulse duration, DSP_INT0 low (synchronous)

2H+1

tw(INTL)A

Pulse duration, DSP_INT0 low (asynchronous)

tw(INTL)WKP

Pulse duration, DSP_INT0 low for IDLE2/IDLE3 wakeup

tsu(INT)

Setup time, DSP_INT0 before DSP_CLKOUT low†

† The external interrupt is synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs with consecutive falling

edges of DSP_CLKOUT. The input to the interrupt pin is required to represent a 1-0-0 sequence at the timing that is corresponding to three

DSP_CLKOUT sampling sequences.

DSP_INT0

DSP_CLKOUT

th(INT)

tsu(INT)

tw(INTL)A

tw(INTH)A

Figure 6--12. Interrupt Timing

TNETV1002IDZHK Datasheet(PDF) 71 Page - Texas Instruments