SP5730ASLASHKGSLASHMP2S datasheet(4/12 Pages) ZARLINK

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SP5730 Datasheet

Write mode

With reference to Table 3, bytes 2 and 3 contain frequency

information bits 214-20 inclusive. Bytes 4 and 5 control

the reference divider ratio (see Table 2), charge pump

setting (see Table 7), REF/COMP output (see Table 8),

output ports and test modes (see Table 6).

After reception and acknowledgement of a correct

address (byte 1), the first bit of the following byte

determines whether the byte is interpreted as a byte 2 or

4, a logic ‘0’ indicating byte 2, and a logic ‘1’ indicating

byte 4. Having interpreted this byte as either byte 2 or 4,

the following data byte will be interpreted as byte 3 or 5

respectively. Having received two complete data bytes,

additional data bytes can be entered, where byte

interpretation follows the same procedure, without re-

addressing the device. This procedure continues until a

STOP condition is received. The STOP condition can be

generated after any data byte; if, however, it occurs during

a byte transmission, the previous byte data is retained.

To facilitate smooth fine tuning, the frequency data bytes

are only accepted by the device after all 15 bits of

frequency data have been received, or after the generation

of a STOP condition.

Read mode

When the device is in read mode, the status byte read

from the device takes the form shown in Table 4.

Bit 1 (POR) is the power-on reset indicator, and this is set

to a logic ‘1’ if the VCC supply to the device has dropped

below 3V (at 25

°C ), e.g. when the device is initially turned

on. The POR is reset to ‘0’ when the read sequence is

terminated by a STOP command. When POR is set high

this indicates the programmed information may be

corrupted and the device reset to power up condition.

Bit 2 (FL) indicates whether the device is phase locked, a

logic’1’is present if the device is locked, and a logic ‘0’ if it

is not.

Programable features

• RF programmable divider Function as described

above.

• Reference programmable divider Function as

described above.

• Charge pump current The charge pump current can

be programmed by bits C1 and C0 within data byte 5,

as defined in Table 7.

• Test mode The test modes are invoked by setting bits

RE, RS, T1 and T0 as described in Table 6.

• Reference/Comparison frequency output The

reference frequency fREF or comparison frequency

fCOMP can be switched to the REF/COMP output,

function as defined in Table 8. RE and RS default to

logic’1’during device power up, thus enabling the

comparison frequency fCOMP at the REF/COMP output.

Table 2 - Reference division ratios

Division ratio

128

256

Illegal state

160

320

Illegal state

192

384

Illegal state

112

224

448

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