VSP1221 datasheet(13/26 Pages) TI

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Blanking Register

Signal Polarity Register

(1)

VSP1221

SLES012A – SEPTEMBER 2001 – REVISED JULY 2004

SD15

SD0

SD14

SD13

SD12

SD11

SD10

SD9

SD8

SD7

SD6

SD5

SD4

SD3

SD2

SD1

MSB

LSB

RD/WR

MSB

BLKGVAL

LSB

Address

Data

BIT

NAME

DEFAULT

DESCRIPTION

VALUE

SD0-

BLKGVAL

All 0

Output data when BLKG (pin 19) is low

DS9

Code

Output data (blanking level)

0000000000

LSB

0000000001

LSB

1111111110

1022

LSBs

1111111111

1023

LSBs

SD8-

Reserved

All 0

Reserved

SD9

SD15

SD0

SD14

SD13

SD12

SD11

SD10

SD9

SD8

SD7

SD6

SD5

SD4

SD3

SD2

SD1

MSB

LSB

RD/WR

Reserved

SPDZ

ADCZ

OBZ

BLZ

CLZ

Address

Data

(1)

For this register to take effect, bit SD4 of timing register 1 must be 0.

BIT

NAME

DEFAULT VALUE

DESCRIPTION

SD0

CLZ

CLZ = 0, CLPDM (pin 23) = active low

CLZ = 1, CLPDM (pin 23) = active high

SD1

BLZ

BLZ = 0, BLKG (pin 19) = active low

BLZ = 1, BLKG (pin 19) = active high

SD2

OBZ

OBZ = 0, CLPOB (pin 20) = active low

OBZ = 1, CLPOB (pin 20) = active high

SD3

ADCZ

ADCZ = 0, ADCCLK (pin 16) = active low

ADCZ = 1, ADCCLK (pin 16) = active high

SD4

SPDZ

SPDZ = 0, SHP (pin 21) = active low, SHD (pin 22) = active low

SPDZ = 1, SHP (pin 21) = active high, SHD (pin 22) = active high

SD5-SD9

Reserved

All 0

Reserved

VSP1221 Datasheet(PDF) 13 Page - Texas Instruments

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