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MIC2198BML Datasheet(PDF) 13 Page - Micrel Semiconductor |
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MIC2198BML Datasheet(HTML) 13 Page - Micrel Semiconductor |
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13 / 15 page ![]() November 2004 13 MIC2198 MIC2198 Micrel The input capacitor must be rated for the input current ripple. The RMS value of input capacitor current is determined at the maximum output current. Assuming the peak-to-peak induc- tor ripple current is low: II D (1 D) C (rms) OUT(max) IN ≈ ×× − The power dissipated in the input capacitor is: PI R DISS(C ) C (rms) ESR(C ) IN IN 2 IN =× Voltage Setting Components The MIC2198 requires two resistors to set the output voltage as shown in Figure 6. Error Amp 3 MIC2198 FB VREF 0.8V R2 R1 Figure 6. Voltage-Divider Configuration The output voltage is determined by the equation: VV 1 R1 R2 O REF =× + ⎛ ⎝ ⎜ ⎞ ⎠ ⎟ Where: V REF for the MIC2198 is typically 0.8V. A typical value of R1 can be between 3k and 10k. If R1 is too large it may allow noise to be introduced into the voltage feedback loop. If R1 is too small in value it will decrease the efficiency of the power supply, especially at low output loads. Once R1 is selected, R2 can be calculated using: R2 VR1 VV REF O REF = × − Voltage Divider Power Dissipation The reference voltage and R2 set the current through the voltage divider. I V R2 DIVIDER REF = The power dissipated by the divider resistors is: P (R1 R2) I DIVIDER DIVIDER 2 =+ × Efficiency Calculation and Considerations Efficiency is the ratio of output power to input power. The difference is dissipated as heat in the buck converter. Under light output load, the significant contributors are: • Supply current to the MIC2198 • MOSFET gate-charge power (included in the IC supply current) • Core losses in the output inductor To maximize efficiency at light loads: • Use a low gate-charge MOSFET or use the small- est MOSFET, which is still adequate for maximum output current. • Use a ferrite material for the inductor core, which has less core loss than an MPP or iron power core. Under heavy output loads the significant contributors to power loss are (in approximate order of magnitude): • Resistive on-time losses in the MOSFETs • Switching transition losses in the MOSFETs • Inductor resistive losses • Current-sense resistor losses • Input capacitor resistive losses (due to the capaci- tors ESR) To minimize power loss under heavy loads: • Use logic-level, low on-resistance MOSFETs. Mul- tiplying the gate charge by the on-resistance gives a figure of merit, providing a good balance be- tween low and high load efficiency. • Slow transition times and oscillations on the volt- age and current waveforms dissipate more power during turn-on and turnoff of the MOSFETs. A clean layout will minimize parasitic inductance and capacitance in the gate drive and high current paths. This will allow the fastest transition times and waveforms without oscillations. Low gate- charge MOSFETs will transition faster than those with higher gate-charge requirements. • For the same size inductor, a lower value will have fewer turns and therefore, lower winding resis- tance. However, using too small of a value will require more output capacitors to filter the output ripple, which will force a smaller bandwidth, slower transient response and possible instability under certain conditions. • Lowering the current-sense resistor value will de- crease the power dissipated in the resistor. How- ever, it will also increase the overcurrent limit and will require larger MOSFETs and inductor compo- nents. • Use low-ESR input capacitors to minimize the power dissipated in the capacitors ESR. Decoupling Capacitor Selection The 4.7µF decoupling capacitor is used to minimize noise on the V DD pin. The placement of this capacitor is critical to the proper operation of the IC. It must be placed right next to the pins and routed with a wide trace. The capacitor should be a good quality tantalum. An additional 1µF ceramic capacitor may be necessary when driving large MOSFETs with high gate capacitance. Incorrect placement of the V DD decoupling capacitor will cause jitter or oscillations in the switching waveform and large variations in the overcurrent limit. A 0.1µF ceramic capacitor is required to decouple the VIN. The capacitor should be placed near the IC and connected directly to between pin 6 (V IN) and pin 9 (GND). |
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