CS8952T datasheet(41/86 Pages) CIRRUS

41 / 86 page

DS206TPP2

CS8952T

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

CIRRUS LOGIC ADVANCED PRODUCT DATABOOK

Interrupt Mask Register - Address 10h

This register indicates which events will cause an interrupt event on the MII_IRQ pin. Each bit acts as an enable to the interrupt.

Thus, when set, the event will cause the MII_IRQ pin to be asserted. When clear, the event will not affect the MII_IRQ pin, but

the status will still be reported via the Interrupt Status Register (address 11h).

CIM Link

Unstable

Link Status

Change

Descrambler

Lock Change

Premature

End Error

DCR

Rollover

FCCR

Rollover

RECR

Rollover

Remote

Loopback

Fault

Reset

Complete

Jabber

Detect

Auto-Neg

Complete

Parallel

Detection

Fault

Parallel

Fail

Remote

Fault

Page

Received

Reserved

BIT

NAME

TYPE

RESET

DESCRIPTION

CIM Link Unstable

Read/Write 0

When set, an interrupt will be generated if an unsta-

ble link condition is detected by the Carrier Integrity

Monitor function.

Note: This bit is disabled, and writes to this bit are

ignored when the National Compatibility Mode bit of

the 10BASE-T Configuration Register (address 1Ch)

is set.

Link Status Change Read/Write 1

When set, an interrupt will be generated each time

the CS8952T detects a change in the link status.

Note: This bit is disabled, and writes to this bit are

ignored when the National Compatibility Mode bit of

the 10BASE-T Configuration Register (address 1Ch)

is set.

Descrambler Lock

Change

Read/Write 0

When set, an interrupt will be generated each time

the 100BASE-TX receive descrambler loses or

regains synchronization with the far-end.

Note: This bit is disabled, and writes to this bit are

ignored when the National Compatibility Mode bit of

the 10BASE-T Configuration Register (address 1Ch)

is set.

Premature End

Error

Read/Write 0

When set, an interrupt will be generated when two

consecutive IDLES are detected in a 100BASE-TX

frame without the End-of-Stream-Delimiter sequence.

Note: This bit is disabled, and writes to this bit are

ignored when the National Compatibility Mode bit of

the 10BASE-T Configuration Register (address 1Ch)

is set.

CS8952T Datasheet(PDF) 41 Page - Cirrus Logic

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