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CY28301
Document #: 38-07011 Rev. *C
Page 8 of 15
Bit 1
Reserved
0
Reserved
Bit 0
Reserved
0
Reserved
Byte 10: Reserved Register
Bit
Name
Default
Description
Bit 7
CPU_Skew2
0
CPU skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Bit 6
CPU_Skew1
0
Bit 5
CPU_Skew0
0
Bit 4
SDRAM_Skew2
0
SDRAM skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Bit 3
SDRAM_Skew1
0
Bit 2
SDRAM_Skew0
0
Bit 1
AGP_Skew1
0
AGP skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
Bit 0
AGP_Skew0
0
Byte 11: Reserved Register
Bit
Name
Default
Pin Description
Bit 7
Reserved
0
Reserved
Bit 6
Reserved
0
Reserved
Bit 5
Reserved
0
Reserved
Bit 4
Reserved
0
Reserved
Bit 3
Reserved
0
Reserved
Bit 2
Reserved
0
Reserved
Bit 1
Reserved
0
Reserved
Bit 0
Reserved
0
Reserved
Byte 12: Reserved Register
Bit
Name
Default
Pin Description
Bit 7
Reserved
0
Reserved
Bit 6
Reserved
0
Reserved
Bit 5
Reserved
0
Reserved
Bit 4
Reserved
0
Reserved
Bit 3
Reserved
0
Reserved
Bit 2
Reserved
0
Reserved
Bit 1
Reserved
0
Reserved
Bit 0
Reserved
0
Reserved
Byte 9: Reserved Register (continued)
Bit
Name
Default
Pin Description
Mexican ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
