HT6P20X Series

Rev. 1.40

4

June 20, 2003

S t a n d b y m o d e

T r a n s m i s s i o n

e n a b l e d ?

N o

N o

Y e s

Y e s

A d d r e s s / d a t a w o r d s

t r a n s m i t t e d

T r a n s m i s s i o n

s t i l l e n a b l e d

A d d r e s s / d a t a w o r d s

t r a n s m i t t e d

c o n t i n u o u s l y

P o w e r o n

P G M = 0 ?

N o

Y e s

P r o g r a m m i n g

m o d e

N o

Y e s

P r o g r a m m i n g

c o m p l e t e d ?

N o t e : O n e t i m e p r o g r a m m a b l e

The HT6P20A/B/D detects the logic state of the internal programmed address and the external data pins, and then trans-

mits the detected information during the code period. Each address/data bit can be set to one of the following two logic

states:

Flowchart

" O n e "

" Z e r o "

f o s c

A d d r e s s /

D a t a b i t