PLL1705

PLL1706

SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002

3.3-V DUAL PLL MULTICLOCK GENERATOR

FEATURES

96 kHz)

96 kHz)

PLL1706: Serial Control

Product

APPLICATIONS

DESCRIPTION

loop (PLL) multiclock generators. The PLL1705 and

PLL1706 can generate four system clocks from a 27-MHz

reference input frequency. The clock outputs of the

PLL1705 can be controlled by sampling frequency-control

pins and those of the PLL1706 can be controlled through

serial-mode control pins. The device gives customers both

cost

and

space

savings

by

eliminating

external

components and enables customers to achieve the very

low-jitter performance needed for high performance audio

DACs and/or ADCs. The PLL1705 and PLL1706 are ideal

for MPEG-2 applications which use a 27-MHz master

clock such as DVD players, DVD add-on cards for

multimedia PCs, digital HDTV systems, and set-top

boxes.

FUNCTIONAL BLOCK DIAGRAM

Mode Control Interface

( ): PLL1706

XT1

(ML)

SR

(MC)

FS2

(MD)

FS1

CSEL

PLL2

PLL1

OSC

XT2

MCKO1

MCKO2

SCKO0

Divider

Divider

Divider

SCKO1

SCKO2

SCKO3

Reset

Power Supply

VCC AGND VDD1–3 DGND1–3

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright

 2002, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

†The PLL1705 and PLL1706 use the same die and they are electrically identical except for mode control.