DF1706ESLASH2K datasheet(12/16 Pages) TI

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DF1706

SBAS182

MODE0 Register

The MODE0 register is used to set the attenuation data for

the left output channel, or DOL (pin 24).

When ATC = 1 (Bit B2 of Register MODE3 = 1), the left

channel attenuation data AL[7:0] is used for both the left

and right channel attenuators.

When ATC = 0, (Bit B2 of Register MODE3 = 0), left

channel attenuation data is taken from AL[7:0] of register

MODE0, and right channel attenuation data is taken from

AR[7:0] of register MODE1.

AL[7:0]

Left Channel Attenuator Data, where AL7 is the

MSB and AL0 is the LSB.

Attenuation Level is given by:

ATTEN = 0.5 • (DATA – 255)dB

For DATA = FFH, ATTEN = –0dB

For DATA = FEH, ATTEN = –0.5dB

For DATA = 01H, ATTEN = –127.5dB

For DATA = 00H, ATTEN = infinity = Mute

LDL

Left Channel Attenuation Data Load Control.

This bit is used to simultaneously set attenua-

tion levels of both the left and right channels.

When LDL = 1, the left channel output level is

set by the data in AL[7:0]. The right channel

output level is set by the data in AL[7:0], or the

most recently programmed data in bits AR[7:0]

of register MODE1.

When LDL = 0, the left channel output data

remains at its previously programmed level.

MODE1 Register

The MODE1 register is used to set the attenuation data for

the right output channel, or DOR (pin 23).

When ATC = 1 (Bit B2 of Register MODE3 = 1), the left

channel attenuation data AL[7:0] of register MODE0 is

used for both the left and right channel attenuators.

When ATC = 0, (Bit B2 of Register MODE3 = 0), left

channel attenuation data is taken from AL[7:0] of register

MODE0, and right channel attenuation data is taken from

AR[7:0] of register MODE1.

AR[7:0]

Right Channel Attenuator Data, where AR7 is

the MSB and AR0 is the LSB. Attenuation

Level is given by:

ATTEN = 0.5 • (DATA – 255)dB

For DATA = FFH, ATTEN = –0dB

For DATA = FEH, ATTEN = –0.5dB

For DATA = 01H, ATTEN = –127.5dB

For DATA = 00H, ATTEN = infinity = Mute

LDR

Right Channel Attenuation Data Load Control.

This bit is used to simultaneously set attenua-

tion levels of both the left and right channels.

When LDR = 1, the right channel output level

is set by the data in AR[7:0], or by the data in

bits AL[7:0] of register MODE0. The left chan-

nel output level is set to the most recently

programmed data in bits AL[7:0] of register

MODE0.

When LDR = 0, the right channel output data

remains at its previously programmed level.

MODE2 Register

The MODE2 register is used to program various functions:

MUT

Soft Mute Function.

When MUT = 0, Soft Mute is ON for both left

and right channels.

When MUT = 1, Soft Mute is OFF for both left

and right channels.

DEM

Digital De-Emphasis Function.

When DEM = 0, de-emphasis is OFF.

When DEM = 1, de-emphasis is ON.

x4 Oversampling Rate Selection

When x4 = 0, 8fS Sampling Rate Operation

When x4 = 1, 4fS Sampling Rate Operation

IW[1:0]

Input Data Format and Word Length.

I2S

IW1

IW0

Description

16-Bit Data, Standard

Format (MSB-First,

Right-Justified)

20-Bit Data, Standard

Format

24-Bit Data, Standard

Format

24-Bit Data, MSB-First,

Left-Justified

16-Bit Data, I2S Format

24-Bit Data, I2S format

Reserved

OW[1:0]

Output Data Word Length.

OW1 OW0

Description

16-Bit Data, MSB-First

18-Bit Data, MSB-First

20-Bit Data, MSB-First

24-Bit Data, MSB-First

MODE3 Register

The MODE3 register is used to program various functions.

I2S

Input Data Format.

When I2S = 0, standard or left-justified formats

are enabled.

When I2S = 1, the I2S formats are enabled.

LRP

LRCIN Polarity Selection.

When LRP = 0, left channel is HIGH and right

channel is LOW.

When LRP = 1, left channel is LOW and right

channel is HIGH.

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