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AS7C1024A-20JC Datasheet(PDF) 4 Page - Alliance Semiconductor Corporation

No. de pieza AS7C1024A-20JC
Descripción Electrónicos  5V/3.3V 128KX8 CMOS SRAM (Evolutionary Pinout)
PDF  9 Pages
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Fabricante Electrónico  ALSC [Alliance Semiconductor Corporation]
Página de inicio  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS7C1024A-20JC Datasheet(HTML) 4 Page - Alliance Semiconductor Corporation

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AS7C1024A
AS7C31024A
9/26/02; 0.9.9
Alliance Semiconductor
P. 4 of 9
®
Key to switching waveforms
Read waveform 1 (address controlled)
Read waveform 2 (CE1, CE2, and OE controlled)
Read cycle (over the operating range)
Parameter
Symbol
-10
-12
-15
-20
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Read cycle time
tRC
10
–
12
–
15
–
20
–
ns
Address access time
tAA
–
10
–
12
–
15
–
20
ns
3
Chip enable (CE1) access time
tACE1
–
10
–
12
–
15
–
20
ns
3, 12
Chip enable (CE2) access time
tACE2
–
10
–
12
–
15
–
20
ns
3, 12
Output enable (OE) access time
tOE
–
5
–6–7–8
ns
Output hold from address change
tOH
2–3–3–3
–
ns
5
CE1 Low to output in low Z
tCLZ1
0–0–0–0
–
ns
4, 5, 12
CE2 High to output in low Z
tCLZ2
0–0–0–0
–
ns
4, 5, 12
CE1 Low to output in high Z
tCHZ1
–
3
–3–4–5
ns
4, 5, 12
CE2 Low to output in high Z
tCHZ2
–
3
–3–4–5
ns
4, 5, 12
OE Low to output in low Z
tOLZ
0–0–0–0
–
ns
4, 5
OE High to output in high Z
tOHZ
–
3
–3–4–5
ns
4, 5
Power up time
tPU
0–0–0–0
–
ns
4, 5, 12
Power down time
tPD
–
10
–
12
–
15
–
20
ns
4, 5, 12
Undefined / don’t care
Falling input
Rising input
Address
DOUT
Data valid
tOH
tAA
tRC
supply
Current
CE2
OE
DOUT
tOE
tOLZ
tACE1, tACE2
tCHZ1, tCHZ2
tCLZ1, tCLZ2
tPU
tPD
ICC
ISB
50%
50%
Data valid
tRC1
CE1
tOHZ



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