MP7614

2

Rev. 2.00

ORDERING INFORMATION

Package

Type

Temperature

Range

Part No.

Ceramic Dip

MP7614KD

Ceramic Dip

MP7614TD*

Plastic Dip

MP7614JN

Plastic Dip

MP7614KN

–40 to +85

–55 to +125

+4

+2

+2

+2

+0.8

+0.8

+0.8

+0.8

+4

+2

+2

+2

–40 to +85

–40 to +85

SOIC

MP7614KS

+0.8

–40 to +85

+2+2

INL

(LSB)

Gain Error

(% FSR)

DNL

(LSB)

*Contact factory for non-compliant military processing

PIN CONFIGURATIONS

GND

(MSB) BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 14 (LSB)

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

20 Pin CDIP, PDIP (0.300”)

D20, N20

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

20

1

11

10

2

3

4

5

6

7

15

14

13

12

17

16

8

9

19

18

20 Pin SOIC (Jedec, 0.300”)

S20

BIT 14 (LSB)

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

GND

(MSB) BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

See Packaging Section for Package Dimensions

Current Output 1

Current Output 2

3

GND

Ground

4

BIT 1

Data Input Bit 1 (MSB)

5

BIT 2

Data Input Bit 2

6

BIT 3

Data Input Bit 3

7

BIT 4

Data Input Bit 4

8

BIT 5

Data Input Bit 5

9

BIT 6

Data Input Bit 6

10

BIT 7

Data Input Bit 7

PIN OUT DEFINITIONS

PIN NO.

NAME

DESCRIPTION

11

BIT 8

Data Input Bit 8

12

BIT 9

Data Input Bit 9

13

BIT 10

Data Input Bit 10

14

BIT 11

Data Input Bit 11

15

BIT 12

Data Input Bit 12

16

BIT 13

Data Input Bit 13

17

BIT 14

Data Input Bit 14 (LSB)

18

Positive Power Supply

19

Reference Input Voltage

20

Internal Feedback Resistor

PIN NO.

NAME

DESCRIPTION