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CY28158
Document #: 38-07039 Rev. *B
Page 5 of 10
IDD3
3.3V Power Supply Cur-
rent
VDDA/VDD33 = 3.465V, VDD25 = 2.625V, FCPU = 133 MHz
160
mA
IDDPD2
2.5V Shutdown Current
VDDA/VDD33 = 3.465V, VDD25 = 2.625V
100
µA
IDDPD3
3.3V Shutdown Current
VDDA/VDD33 = 3.465V, VDD25 = 2.625V
200
µA
Switching Characteristics[5] Over the Operating Range
Parameter
Output
Description
Test Conditions
Min.
Max.
Unit
t1
All
Output Duty Cycle[6]
t1A/t1B
45
55
%
t2
CPU,
IOAPIC
Rising Edge Rate
Between 0.4V and 2.0V
1.0
4.0
V/ns
t2
48MHZ, REF
Rising Edge Rate
Between 0.4V and 2.4V
0.5
2.0
V/ns
t2
PCI, 3V66
Rising Edge Rate
Between 0.4V and 2.4V
1.0
4.0
V/ns
t3
CPU,
IOAPIC
Falling Edge Rate
Between 2.0V and 0.4V
1.0
4.0
V/ns
t3
48MHZ, REF
Falling Edge Rate
Between 2.4V and 0.4V
0.5
2.0
V/ns
t3
PCI, 3V66
Falling Edge Rate
Between 2.4V and 0.4V
1.0
4.0
V/ns
t6
CPU
CPU-CPU Skew
Measured at 1.25V
175
ps
t8
IOAPIC
IOAPIC-IOAPIC Skew
Measured at 1.25V
250
ps
t9
3V66
3V66-3V66 Skew
Measured at 1.5V
250
ps
t10
PCI
PCI-PCI Skew
Measured at 1.5V
500
ps
t11
CPU, 3V66
CPU-3V66 Clock Skew
CPU leads. Measured at 1.25V for
2.5V clocks and 1.5V for 3.3V clocks
01.5
ns
t12
3V66, PCI
3V66-PCI Clock Skew
3V66 leads. Measured at 1.5V
0.5
2.5
ns
t13
CPU, IOAPIC
CPU-IOAPIC Clock Skew
CPU leads. Measured at 1.25V
1.5
4
ns
CPU
Cycle-Cycle Clock Jitter
With all outputs running
150
ps
IOAPIC
Cycle-Cycle Clock Jitter
500
ps
48MHZ
Cycle-Cycle Clock Jitter
500
ps
3V66
Cycle-Cycle Clock Jitter
500
ps
REF
Cycle-Cycle Clock Jitter
1000
ps
CPU, PCI
Settle Time
CPU and PCI clock stabilization from
power-up
3ms
Notes:
4.
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
5.
All parameters specified with loaded outputs.
6.
Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
Electrical Characteristics Over the Operating Range (continued)
Parameter
Description
Test Conditions
Min. Max. Unit
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