LE25S161 datasheet(21/54 Pages) ONSEMI

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LE25S161

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10-5-2. High-Speed Read command (RDHS)

Maximum Clock frequency: 70MHz

This command is for reading data out at the high frequency operation.

"Figure 7. High-Speed Read (RDHS)" shows the timing waveforms.

The sequence of RDHS operation :

CS goes to low  input RDHS command (0Bh)  3 Byte address (A23-A0) input on SI

 1 byte dummy cycle  the corresponding data out on SO

 continuous data out (n-byte) 

 completed by CS=high

* The data output starts from the falling edge of SCK(39th clock)

The Address is latched on rising edge of SCK. It is necessary to add 1 dummy byte cycle after address is latched, and the

corresponding data is shifted out on SO by the falling edge of SCK. The address is automatically incremented to the next

higher address after each byte data is shifted out. If the SCK input is continued after the internal address arrives at the

highest address (1FFFFFh), the internal address returns to the lowest address (000000h). By setting CS to high, the device

is deselected, and the read cycle is completed. While the device is deselected, the output pin SO is in a high-impedance

state.

Figure 7. High-Speed Read (RDHS)

● Address A23 to A21 are "Don't care".

Add

(A7-A0)

Add

(A15-A8)

Add

(A23-A16)

Byte 3

Byte 2

Byte 1

High Impedance

DATA

SCK

0Bh

MSB

31 32

39 40

47 48

Mode3

Mode0

8CLK

MSB

LE25S161 Datasheet(PDF) 21 Page - ON Semiconductor