EP7212 datasheet(21/136 Pages) CIRRUS

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EP7212

DS474PP1

3.2

State Control

The EP7212 supports the following Power Man-

agement States: Operating, Idle, and Standby (see

Figure 3). The normal program execution state is

the Operating State; this is a full performance state

where all of the clocks and peripheral logic are en-

abled. The Idle State is the same as the Operating

State with the exception of the CPU clock being

halted, and an interrupt or wakeup will return it

back to the Operating State. The Standby State has

the lowest power consumption of the three states.

By selecting this mode the main oscillator shuts

down, leaving only the Real Time Clock and its as-

sociated logic powered. It is important when the

EP7212 is in Standby that all power and ground

pins remain connected to power and ground in or-

der to have a proper system wake-up. The only

state that Standby can transition to is the Operating

State.

In the description below, the RUN/CLKEN pin can

be used either for the RUN functionality, or the

CLKEN functionality to allow an external oscilla-

tor to be disabled in the 13 MHz mode. Either RUN

or CLKEN functionality can be selected according

to the state of the CLKENSL bit in the SYSCON2

ripheral status in various power management

states.

3.2.1

Standby State

The Standby State equates to the system being

switched "off" (i.e., no display, and the main oscil-

lator is shut down). When the 18.432–73.72 MHz

mode is selected, the PLL will be shut down. In the

13 MHz mode, if the CLKENSL bit is set low, then

the CLKEN signal will be forced low and can, if re-

quired, be used to disable an external oscillator.

In the Standby State, all the system memory and

state is maintained and the system time is kept up-

to-date. The PLL/on-chip oscillator or external os-

cillator is disabled and the system is static, except

for the low power watch crystal (32 kHz) oscillator

and divider chain to the RTC and LED flasher. The

RUN signal is driven low, therefore this signal can

be used externally in the system to power down

other system modules.

Whenever the EP7212 is in the Standby State, the

external address and data buses are forced low in-

ternally by the RUN signal. This is done to prevent

peripherals that are powered down from draining

current. Also, the internal peripheral’s signals get

set to their Reset State.

When first powered, or reset by the nPOR (Power

On Reset, active low) signal, the EP7212 is forced

into the Standby State. This is known as a cold re-

set, and when leaving the Standby State after a cold

reset, external wake up is the only way to wake up

the device. When leaving the Standby State after

non-cold reset conditions (i.e., the software has

forced the device into the Standby State), the tran-

sition to the Operating State can be caused by a ris-

ing edge on the WAKEUP input signal or by an

enabled interrupt. Normally, when entering the

Standby State from the Operating State, the soft-

ware will leave some interrupt sources enabled.

NOTE:

The CPU cannot be awakened by the TINT,

WEINT, and BLINT interrupts when in the

Standby State.

Typically, software writes to the Standby internal

memory location to cause the transition from the

Figure 3. State Diagram

Standby

Operating

Idle

Interrupt or rising wakeup

Write to standby location,

power fail, or user reset

Write to halt location

nPOR, power fail,

or user reset

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